Self-aligned Patterning Research Articles

Three-Mask Elevated-Metal Metal-Oxide Thin-Film Transistor With Self-Aligned Definition of the Active Island

Bottom-gate thin-film transistors (TFTs) are currently fabricated using either a three-mask back-channel-etched (BCE) or, with an additional mask for the definition of an etch-stop (ES) layer, a four-mask technology. The former offers a lower cost of manufacturing and a higher resolution, while the latter provides better device characteristics in terms of both performance and reliability. Presently reported is a three-mask process for realizing an elevated-metal metal-oxide TFT employing self-aligned patterning of the active island, also inherently incorporating an ES layer. This technology offers a TFT that combines the same protection of the channel, and hence, the good characteristics of an ES TFT, with the lower cost, reduced parasitic overlap capacitance, and smaller device-footprint of a BCE TFT.

Poly-Si(O)x passivating contacts for high-efficiency c-Si IBC solar cells

Highest conversion efficiency in crystalline silicon (c-Si) solar cells can be enabled by quenching minority carriers’ recombination at c-Si/contact interface owing to carrier-selective passivating contacts. With the semi-insulating poly-crystalline silicon (SIPOS, poly-Si) a very good passivation of c-Si surfaces was obtained. We have explored these passivating structures on IBC solar cells and obtained over 22% efficiency with over 23% within reach on the short term. We present in detail the passivation quality of p-type and n-type ion-implanted LPCVD poly-crystalline silicon (poly-Si) and its relation to the doping profile. Optimized poly-Si layers in the role of emitter and BSF showed excellent passivation (J0,emitter = 11.5 fA/cm2 and J0,BSF = 4.5 fA/cm2) and have been deployed in FSF-based IBC c-Si solar cells using a simple self-aligned patterning process. Applying an optimized passivation of FSF by PECVD a-Si:H/SiNx layer (J0,FSF = 6.5 fA/cm2) leads to a cell with efficiency of 22.1% (VOC = 709 mV, JSC = 40.7 mA/cm2, FF = 76.6%). Since over 83% FF has been reached with adjusted metallization technology on similar IBC structures, we believe 23% efficiency is within reach on the short term. Further improvement, especially at JSC level, is expected by deploying less absorbing carrier-selective passivating contacts based on poly-Si or wide bandgap poly-SiOx layers (J0 ~ 10 fA/cm2).

A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning

Self-aligned triple patterning (SATP) lithography is one of the most promising technologies for next-generation semiconductor manufacturing process. Self-aligned patterning attracts much interest because of its significant advantage over the litho-etch-litho-etch patterning in reducing the overlay problem in lithography. However, pattern decomposition in SATP is challenging due to its counterintuitive mask synthesis. It remains relatively unstudied and its practical solutions remain to be proposed. This paper proposes an effective algorithm for SATP layout decomposition without grid-based quantization and thus substantially reduces the number of variables and constraints in solution search. Boolean satisfiability (SAT) and integer linear programming (ILP) are exploited for efficient computation. In addition to deriving high-quality layout decomposition solutions with overlay minimization, our method also allows nondecomposable spot identification to facilitate layout rectification. Experimental results demonstrate the superiority of our method compared to prior work and show the relative advantages of SAT and ILP formulations.

Benefits of atomic-level processing by quasi-ALE and ALD technique

A new technology has been developed using the atomic layer etching (ALE) and atomic layer deposition (ALD) concepts. It has been applied to self-aligned contacts (SAC) and patterning processes, for the sub 7 nm technology generation. In the SAC process, ultra-high selectivity of SiO2 etching towards SiN is required, for which we have developed quasi-ALE technique for SiO2 etching. We were able to significantly improve the trade-off between the etching ability of SiO2 on the micro slit portions and SiN selectivity. Quasi-ALE precisely controls the reaction layer thickness of the surface, by controlling the radical flux and ion flux independently, and hence enables etching at lower ion energies (Ei < 250 eV). On the other hand, in the patterning processes, the shrinking of critical dimensions (CD) without loading is mandatory. Therefore, we developed a new process flow that combines ALD technique and etching. With this method, we were able to achieve CD shrinking at atomic-layer level precision for various patterns, without causing CD loading. In addition, we were also able to uniformly control the CD shrinkage amount across the whole wafer. This is because this technique takes advantage of the deposition step which is independent of the pattern density and the location on the wafer by self-limited reactions.

Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing

Because of the delay of the next-generation lithography technologies, self-aligned double patterning (SADP) has become one of the major lithography solutions for sub-20-nm technology nodes. For advanced sub-10-nm nodes, self-aligned quadruple patterning (SAQP) or even self-aligned octuple patterning will be required. Due to considerable design complexity and unmanageable process variation, 1-D grid-based layout structure will be adopted, which can be achieved with sophisticated self-aligned multiple patterning (SAMP) process with the use of a cut mask. However, cut masks for arbitrary layouts are hardly manufacturable, because cut mask rules are limited by conventional 193-nm lithography. To the best of our knowledge, most of the existing SADP- and SAQP-aware detailed routers would fail to generate cut mask-friendly routing results for general SAMP. In this paper, we propose the first work of cut mask optimization with wire planning in SAMP full-chip routing. We first identify cut mask-aware routing rules to guide our router. Then, cut mask-aware wire planning, detailed routing, and postlayout modification techniques are proposed in the routing flow. Experimental results show that the proposed routing algorithms are effective in generating routing results with optimized cut masks.

A self-aligned high resolution patterning process for large area printed electronics

A facile and high resolution self-aligned patterning process compatible with directional coating processes is reported for manufacturing printed electronic devices.

Self-aligned patterning of conductive films on plastic substrates for electrodes of flexible electronics

We report a reliable and low-cost self-aligned patterning process for the formation of conducting polymer electrodes with a high resolution on flexible plastic substrates.

(Invited) Plasma-Enhanced Quasi-ALE and ALD Processing for Leading-Edge Microfabrication

We introduce a state-of-the-art self-aligned contact (SAC) process and patterning process developed by new patterning technology using Atomic Layer Etch (ALE) and Atomic Layer Deposition (ALD) towards 5/7nm generation. SAC process is known to require SiO2 etching capability with ultra-high selectivity to SiN. We developed Quasi-ALE technique to improve ALE process to make it more suitable for SiO2 Etch. By adopting this technology to SAC process, the conventional trade-offs between fine process control and SiO2 selectivity to SiN in the fine slit pattern is significantly improved. On the other hand, in the patterning process, CD shrink technique without CD loading is one of the key requirements. By integrating ALD process into the etching flow, we developed a process that can control the CD shrink amount in the atomic layer level without causing CD loading.

Semiconductor scaling via self-aligned block patterning

Semiconductor scaling via self-aligned block patterning

Ink-jet printing technology enables self-aligned mould patterning for electroplating in a single step

We present a new self-aligned, mask-free micro-fabrication method with which to form thick-layered conductive metal micro-structures inside electroplating moulds. Seed layer patterning for electroplating was performed by ink-jet printing using a silver nano-particle ink deposited on SU-8 or Ordyl SY permanent resist. The silver ink contact angle on SU-8 was adjusted by oxygen plasma followed by a hard bake. Besides functioning as a seed layer, the printed structures further served as a shadow mask during patterning of electroplating moulds into negative photoresist. The printed silver tracks remained in strong adhesion to the substrate when exposed to the acidic chemistry of the electroplating bath. To demonstrate the process, we manufactured rectangular, low-resistivity planar micro-coils for use in magnetic resonance microscopy. MRI images of a spring onion with an in-plane resolution down to 10 µm × 10 µm were acquired using a micro-coil on an 11.7 T MRI scanner.

Layout pattern-driven design rule evaluation

With the use of subwavelength photolithography, some layouts can have low printability and, accordingly, low yield due to the existence of bad patterns even though they pass design rule checks. A reasonable approach is to select some of the candidate bad patterns as forbidden. These are the ones with a high yield impact or low routability impact, and these are to be prohibited in the design phase. The rest of the candidate bad patterns may be fixed in the postroute stage in a best-effort manner. The process developers need to optimize the process to be friendly to the patterns of high routability impact. Hence, an evaluation method is required early in the process to assess the impact of forbidding layout patterns on routability. We propose pattern-driven design rule evaluation (pattern-DRE), which can be used to evaluate the importance of patterns for the routability of the standard cells and, accordingly, select the set of bad patterns to forbid in the design. The framework can also be used to compare restrictive patterning technologies [e.g., litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), self-aligned octuple patterning (SAOP)]. Given a set of design rules and a set of forbidden patterns, pattern-DRE generates a set of virtual standard cells; then it finds the possible routing options for each cell without using any of the forbidden patterns. Finally, it reports the routability metrics. We present a few studies that illustrate the use cases of the framework. The first study compares LELE to SADP by using a set of forbidden patterns that are allowed by LELE but not by SADP. Another study compares LELE to extreme ultraviolet lithography from the routability aspect by prohibiting patterns that have LELE native conflicts. In addition, we present a study that investigates the effect of placing the active area of the transistors close to the P/N interface instead of close to the power rails.

Impact of process parameters on pattern formation of the self-aligned multiple patterning process.

Double patterning (DP) and multiple patterning (MP) are techniques employed to extend the useful life of optical lithography through higher density chip transistors. The self-aligned double patterning (SADP) and the self-aligned multiple patterning (SAMP) are promising technologies that can be expanded to 22 nm and 1 x nm patterns for the dynamic random access memory (DRAM) and NAND flash memory devices. It is important to understand how the final pattern is related to each SADP or SAMP step to optimize process parameters and develop those processes. In this paper, the SADP and the SAMP model the optical lithography process and the spacer-aligned process to reduce those complexites and optimize those critical dimension uniformities (CDUs). For the spacer-aligned process, deposition and etching were modeled using a ray-trace algorithm and a level-set method. For the SADP and the SAMP, simulation results similar to the experimental results allow the prediction of self-aligned patterns and the pattern effects of process parameters.

Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning

Multiple patterning lithography is the most likely manufacturing process for sub-32 nm technology nodes. Among different multiple patterning methods, self-aligned patterning has attracted much interest due to its robustness against overlay errors. However, self-aligned patterning compliance is subject to the litho-friendliness of the applied decomposition method. This brief establishes self-aligned triple patterning (SATP) decomposition requirements and proposes a litho-friendly layout decomposition method. First, the major SATP litho-friendliness requirements are explained. In-silico experiments on SATP process indicate that layout features printed by the structural spacers are the most accurate ones. Therefore, we propose an ILP-based decomposition which avoids decomposition conflicts and maximizes the use of structural spacers simultaneously. Experiments reveal that the proposed method improves overlay robustness and line-edge roughness of the attempted test cases.

Sidewall profile engineering for the reduction of cut exposures in self-aligned pitch division patterning

As 193-nm immersion lithography will likely be required to be extended beyond 40-nm half-pitch, multiple patterning lithography will become a necessity in that scenario. We present a cost-effective approach for double patterning with extendibility to sub-10-nm half-pitch division, which is a very promising candidate for advanced logic nodes. Spacers on sufficiently sloped sidewalls directly transferred from a low-contrast photoresist profile can be removed by anisotropic etching. Alternatively, spacer gaps for defining trenches may be prevented from penetrating to the substrate by the use of sloped sidewalls. These sloped sidewalls are defined by attenuated phase-shift mask features, which impart phase shifts other than 180 deg or 0 deg. Loop trimming and sidewall spacer definition are accomplished in a single photomask. In addition, there is now an extra ability to define random, arbitrary breaks in the spacer-defined pattern, without using an extra exposure for specified cuts. In this way, a single exposure using a modified attenuated phase-shift photomask, followed by a low-contrast development process around the sensitivity limit, is sufficient to pattern regularly arranged spacer-defined lines at fixed pitch while including some predetermined line cut locations.

(Invited) Optical Lithography Extension Technique with Multiple-Patterning Process

The double patterning process has become a technology for extending the life of 193-nm immersion lithography. It is the most useful techniques of advancing downscaling in semiconductors and can theoretically be used scale infinitely down. For the self-aligned type of double patterning, such as self-aligned double patterning (SADP), self-aligned triple patterning (SATP), and self-aligned quadruple patterning (SAQP)[1], we have reported that spacer-pattern processing is more difficult than line-pattern processing since the former includes more fluctuating factors, and that improving the performance of the core pattern is essential to solving this problem. Similarly, as calls for even more improvement in line edge roughness (LER) have come to be made, we have investigated the relationship between the core pattern and LER. Thus, given the importance of finding a means of securing pattern fidelity in the core pattern to improve critical dimension uniformity (CDU) and LER,we improved resist contrast resulting in dramatically reduced LER and improved spacer CD uniformity over the wafer surface. This paper presents the results of observing pattern fidelity in the double patterning process from many aspects and the results of testing a technique for high-accuracy management of pattern fidelity.

Process optimization and simplification of self-aligned triple patterning

Graphical abstractDisplay Omitted Highlights? A wet trimming process was developed to shrink mandrel line CD in SATP technique. ? The wet process smoothes out high-frequency components of LER. ? A selective dry etch is used to release the sacrificial spacers. ? CDU and LWR performance have been significantly improved. ? The first full-wafer 18nm L/S CDU and LWR data were reported. Self-aligned triple patterning (SATP) technology offers both improved resolution and design flexibility for scaling integrated circuits down to sub-15nm half pitch. By keeping and designing mandrel patterns which further define the route of the following spacers, SATP process represents a prospective trend that not only drives up the feature density, but also relaxes the overlay requirement with fewer masks and allows quasi-2D design flexibility. In this paper, we shall present the latest research progress made in optimization of existing SATP process to improve its lithographic performance such as CDU and line width roughness. In addition to solving the previously reported problems of etching small mandrels and sacrificial spacers, we also address the issue of reducing SATP process complexity/cost.

Self-aligned patterning method of poly(aniline) for organic field-effect transistor gate electrode

We present a new manufacturing method for the bottom-gate type organic field-effect transistor (OFET) having a self-aligned gate electrode based on conducting poly(aniline). This method utilizes the possibility to turn the insulating emeraldine base (PANI-EB) form of poly(aniline) into the conducting emeraldine salt (PANI-ES) form by using UV exposure and photoacid generator (PAG) material. When the source–drain electrodes are used as the mask layer in the UV exposure step an optimal alignment between the gate electrode and source–drain electrodes can be reached, and the parasitic capacitance of the transistor can be minimized. We anticipate that the proposed concept also simplifies the fabrication of the transistors since no additional processing of the photoresist layers is needed to pattern the gate electrode or the gate insulator layer.

One step self-aligned multilayer patterning process for the fabrication of organic complementary circuits in combination with inkjet printing

Recent development of solution processable organic semiconductors delineates the emergence of a new generation of air-stable, high performance p- and n-type materials. This makes it indeed possible for printed organic complementary circuits (CMOS) to be used in real applications. The main technical bottleneck for organic CMOS to be adopted as the next generation organic integrated circuit is how to deposit and pattern both p- and n-type semiconductor materials with high resolutions at the same time. It represents a significant technical challenge, especially if it can be done for multiple layers without mask alignment. In this paper, we propose a one-step self-aligned fabrication process which allows the deposition and high resolution patterning of functional layers for both p- and n-channel thin film transistors (TFTs) simultaneously. All the dimensional information of the device components is featured on a single imprinting stamp, and the TFT-channel geometry, electrodes with different work functions, p- and n-type semiconductors and effective gate dimensions can all be accurately defined by one-step imprinting and the subsequent pattern transfer process. As an example, we have demonstrated an organic complementary inverter fabricated by 3D imprinting in combination with inkjet printing and the measured electrical characteristics have validated the feasibility of the novel technique.

Self-aligned patterning on a flexible substrate using a dual-tone, thermally activated photoresist

The fabrication of electronic devices on flexible substrates represents an opportunity for the development of flexible display technologies, large area devices, and roll-to-roll manufacturing processes. Traditional photolithography encounters alignment and overlay limitations when applied to flexible substrates. One solution to the overlay challenges is imaging of two device layers in a single lithographic exposure. To enable the simultaneous patterning of two device layers, a new photoresist system was developed. Prior work on dual-tone photoresists introduced formulations capable of storing two independent images, but the reported systems are incompatible with the reactive ion etch processes commonly used today. This paper describes a dual-tone photoresist system that maintains the ability to store two independent latent images, distinguished by the incident exposure light wavelength, simultaneously remaining compatible with reactive ion etch image transfer processes.

Stabilization of the Thermal Decomposition of Poly(Propylene Carbonate) Through Copper Ion Incorporation and Use in Self-Patterning

Incorporation of copper ions into poly(propylene carbonate) (PPC) films cast from γ-butyrolactone (GBL), trichloroethylene (TCE) or methylene chloride (MeCl) solutions containing a photo-acid generator is shown to stabilize the PPC from thermal decomposition. Copper ions were introduced into the PPC mixtures by bringing the polymer mixture into contact with copper metal. The metal was oxidized and dissolved into the PPC mixture. The dissolved copper interferes with the decomposition mechanism of PPC, raising its decomposition temperature. Thermogravimetric analysis shows that copper ions make PPC more stable by up to 50°C. Spectroscopic analysis indicates that copper ions may stabilize terminal carboxylic acid groups, inhibiting PPC decomposition. The change in thermal stability based on PPC exposure to patterned copper substrates was used to provide a self-aligned patterning method for PPC on copper traces without the need for an additional photopatterning registration step. Thermal decomposition of PPC is then used to create air isolation regions around the copper traces. The spatial resolution of the self-patterning PPC process is limited by the lateral diffusion of the copper ions within the PPC. The concentration profiles of copper within the PPC, patterning resolution, and temperature effects on the PPC decomposition have been studied.