Impact of process parameters on pattern formation of the self-aligned multiple patterning process.

Abstract

Double patterning (DP) and multiple patterning (MP) are techniques employed to extend the useful life of optical lithography through higher density chip transistors. The self-aligned double patterning (SADP) and the self-aligned multiple patterning (SAMP) are promising technologies that can be expanded to 22 nm and 1 x nm patterns for the dynamic random access memory (DRAM) and NAND flash memory devices. It is important to understand how the final pattern is related to each SADP or SAMP step to optimize process parameters and develop those processes. In this paper, the SADP and the SAMP model the optical lithography process and the spacer-aligned process to reduce those complexites and optimize those critical dimension uniformities (CDUs). For the spacer-aligned process, deposition and etching were modeled using a ray-trace algorithm and a level-set method. For the SADP and the SAMP, simulation results similar to the experimental results allow the prediction of self-aligned patterns and the pattern effects of process parameters.