Self-aligned Fabrication Process Research Articles

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

A Fully Self-Aligned SiC Trench MOSFET with 0.5 μm Channel Pitch

SiC power MOSFETs have made great progress since the first commercial devices were introduced in 2011, but they are still far from their theoretical limits of performance. At blocking voltages above 1200 V the specific on-resistance is limited by the drift region, but below 1200 V the resistance is dominated by the channel and the substrate, with smaller contributions from the source and JFET regions. Trench MOSFETs have smaller cell area than planar DMOSFETs, and are inherently more scalable. Both Rohm and Infineon devices have cell pitches of about 3 μm per active channel. In this paper we demonstrate a highly self-aligned fabrication process to realize deeply-scaled trench MOSFETs with a cell pitch of 0.5 μm per channel. Since the narrow gate trench is shaped like a letter “I”, we refer to these devices as “IMOSFETs”.

Self-aligned multi-layer X-ray absorption grating using large-area fabrication methods for X-ray phase-contrast imaging

X-ray phase-contrast (XPCi) imaging methods are an emerging medical imaging approach that provide significantly better soft tissue contrast and could function as a viable extension to conventional X-ray, CT, and even some MRI. Absorption gratings play a central role in grating-based XPCi systems, especially because they enable the acquisition of three images in a single exposure: transmission, refraction, and dark-field. An impediment to commercial development and adoption of XPCi imaging systems is the lack of large area, high aspect ratio absorption gratings. Grating technology development, primarily due to technological limitations, has lagged system development and today prevents the scaling up of XPCi system into a footprint and price point acceptable to the medical market. In this work, we report on a self-aligned multi-layer grating fabrication process that can enable large-area X-ray absorption gratings with micron-scale feature sizes. We leverage large-area fabrication techniques commonly employed by the thin-film transistor (TFT) display industry. Conventional ITO-on-glass substrates are used with a patterned film of Cr/Au/Cr that serves as a self-aligned lithography mask for backside exposure. Commonly available SU-8 photoresist is patterned using the backside exposure mask followed by an electroplating step to fill the gaps in the SU-8 with X-ray attenuating material. Consequently, the electroplated patterned material acts as a self-aligned photomask for subsequent SU-8 layer patterning and so forth. The repeatability of the reported process makes it suitable for achieving higher aspect ratio structures and is advantageous over previously reported X-ray LIGA approaches. A prototype three-layer grating, with a thickness of around 40,upmu text{m}, having a visibility of 0.28 at 60,text{kV}_p with a 70,text{mm}times 70,text{mm} active area was fabricated on a 4-inch glass substrate and demonstrated by modifying a commercially available 3D propagation-based XPCi Microscope. The scalable and cost-effective approach to build larger area X-ray gratings reported in this work can help expedite the commercial development and adoption of previously reported Talbot-Lau, speckle-tracking, as well as coded-aperture XPCi systems for large-area clinical and industrial applications.

Recessed-Channel WSe2 Field-Effect Transistor via Self-Terminated Doping and Layer-by-Layer Etching.

Effective channel control with low contact resistance can be accomplished through selective ion implantation in Si and III-V semiconductor technologies; however, this approach cannot be adopted for ultrathin van der Waals materials. Herein, we demonstrate a self-aligned fabrication process based on self-terminated p-doping and layer-by-layer chemical etching to achieve low contact resistance as well as a high on/off current ratio in ultrathin tungsten diselenide (WSe2) field-effect transistors (FETs). Damage-free layer-by-layer thinning of the WSe2 channel is repeated up to a thickness of approximately 1.4 nm, while maintaining the selectively p-doped source/drain regions. The device characteristics of the recessed-channel WSe2 FET are systematically monitored during this layer-by-layer recess-channel process. The WSe2 etching rate is estimated to be 2-3 layers per cycle of oxidation and subsequent chemical etching. The self-terminated tungsten oxide (WOX) layer grown through ultraviolet-ozone treatment induces robust p-doping in the neighboring (or underlying) WSe2 through the electron withdrawal mechanism, which remains in the source/drain regions after channel oxide removal. The adopted self-terminated and self-aligned recess-channel process for ultrathin WSe2 FETs enables the realization of a high on/off output current ratio (>108) and field-effect mobility (∼190 cm2/V·s), while maintaining low contact resistance (0.9-6.1 kΩ·μm) without a postannealing process. The proposed facile and reproducible doping and atomic-layer-etching method for the fabrication of a recessed-channel FET with an ultrathin body can be helpful for high-performance two-dimensional semiconductor devices and is applicable to post-Si complementary metal-oxide semiconductor devices.

Design, fabrication and characterization of TiN sensing film-based ISFET pH sensor

In this work, we report the development of Titanium Nitride (TiN) as a sensing film for Ion-Sensitive Field-Effect Transistor (ISFET)-based pH sensor, which has been deposited using pulsed-DC (Direct Current) magnetron-assisted reactive sputtering process. The material characterization was carried out using various techniques. TiN-gate ISFETs have been fabricated using self-aligned fabrication process by utilizing five levels of lithography steps. The packaging and encapsulation of the sensor has been done by thick film technology and dam-and-fill approach, respectively. The sensor has been characterized and a high sensitivity of nearly 53.98 mV/pH has been obtained. Drift and hysteresis studies were also carried out. The drift rates for different pH buffer solutions 4, 7, 10 are measured to be 0.368 μA/min, 0.296 μA/min, 0.237 μA/min, respectively. A hysteresis value of 0.50 μA has been obtained for pH cycle pH 7 → pH 10 → pH 7 → pH 4 → pH 7.

Self-Aligned Top-Gate Amorphous Zinc-Tin Oxide Thin-Film Transistor With Source/Drain Regions Doped by Al Reaction

A self-aligned fabrication process for top-gate amorphous zinc-tin oxide (a-ZTO) thin-film transistors (TFTs) is developed, in which the source/drain (S/D) doping is realized through depositing a thin aluminum (Al) film on S/D regions and performing a thermal annealing. Results indicate that a chemical oxidation-reduction reaction between Al and a-ZTO films takes place during the thermal annealing process, and shallow donors of oxygen vacancies and metal tin (Sn) interstitials are thus generated. The formed S/D regions have a high carrier concentration over 1 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">20</sup> cm $^{-3}$ , low sheet resistance of 0.57 k Ω/sq, and high thermal stability even in oxygen ambient. The fabricated a-ZTO TFTs exhibit excellent electrical performances, including a low channel-width-normalized S/D resistance of about 7.05 Ω cm, a high field-effect mobility of 15.7 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, a high on/off current ratio of over $10 ^{8}$ , and near-zero turn-on voltage. Moreover, good electrical stability with less than 0.2-V threshold voltage shift under ±30-V gate bias stresses is also achieved.

The IMOSFET: A Deeply-Scaled Fully-Self-Aligned Trench MOSFET

Silicon Carbide (SiC) power MOSFETs have made great progress since the first commercial devices were introduced in 2011, but they are still far from theoretical limits of performance. Above ~1200 V the specific on-resistance is limited by the drift region, but below 1200 V the resistance is dominated by the channel and the substrate, with smaller contributions from the source and the JFET regions. Trench MOSFETs generally have smaller cell area than planar DMOSFETs and are inherently more scalable. In this paper, we describe a highly self-aligned fabrication process to realize deeply-scaled trench MOSFETs with a cell pitch of 0.5 μm per channel. Since the narrow gate trench is shaped like a letter “I”, we refer to these devices as “IMOSFETs.”

Compact and Fabrication-Tolerant Waveguide Bends Based on Quadratic Reflectors

We propose and experimentally demonstrate a broadband, polarization-diverse compact bending design for low-index-contrast waveguides, where light is re-directed via total internal reflection (TIR) on an air-trench quadratic (elliptical or parabolic) reflector surface. Compared to prior work based on flat TIR mirrors, the quadratic reflector design contributes to minimized mode leakage and reduced optical losses, enabling high-density, scalable photonic architectures at the chip and board levels. Moreover, we develop a self-aligned fabrication process where the reflector and the waveguide segments are defined in a single lithography step, thereby circumventing the alignment sensitivity issue common to traditional air trench structures. Our simulations predict bending losses down to <0.14 dB per 90° and 180° bend at 850 nm wavelength, and we experimentally measure broadband losses of ∼0.3 dB per 90° and 180° bend for both TE and TM polarizations in structures fabricated using standard UV lithography.

Self-aligned fabrication process for active membrane in magnetically driven micropump using photosensitive composite

In this paper, we propose a simple fabrication process for an active membrane utilised in the manufacture of micropumps using a photosensitive composite. The composite is developed from a mixture of a negative photoresist (SU-8) and magnetic particles. We evaluated the magnetisation and attractive force of the composites made of Fe3O4, Ni, or Fe. In our experiment, the composite made of Fe (50 wt%) demonstrated the maximum values for magnetisation and attractive force, which were 300 kA m−1 and 2.7 mN, respectively. The processability of the composite (Fe: 50 wt%) showed a saturated exposure thickness of approximately 25 µm, which was caused by the low transmittance for ultraviolet light in the exposure process. We fabricated a micropump using a simple process, which included the manufacture of both of an active membrane and a hollow structure in a one-step self-aligned photolithography process using above processability of the composite. The fabricated device demonstrated that the displacement of the membrane increased with the increase in the applied magnetic field from 10 kA m−1 to 90 kA m−1. The maximum displacement was 4.2 µm at 5 Hz in an applied magnetic field of 90 kA m−1. The flow rate of the micropump was evaluated by particle tracking method and the result was 36.1 nl min−1 at 5 Hz in 90 kA m−1.

Ultrafast Spontaneous Emission from a Slot-Antenna Coupled WSe2 Monolayer

Optical antennas can enhance the spontaneous emission rate from nanoemitters by orders of magnitude, enabling the possibility of an ultrafast, efficient, nanoscale LED. Semiconductors would be the preferred material for such a device to allow for direct high-speed modulation. However, efficient nanoscale devices are challenging to implement because of high surface recombination typical of most III–V materials. Monolayer transition metal dichalcogenides are an attractive alternative to a III–V emitter due to their intrinsically nanoscale dimensions, direct bandgap, and near-ideal surfaces resulting in high intrinsic quantum yield. In this work, we couple a nanostrip (30 nm × 250 nm) monolayer of WSe2 to a cavity-backed optical slot antenna through a self-aligned fabrication process. Photoluminescence, scattering, and lifetime measurements are used to estimate a radiative spontaneous emission rate enhancement of 318× from WSe2 monolayers coupled to on-resonance antennas. Such a huge increase in the spontane...

Self-aligned gate-last process for quantum-well InAs transistor on insulator

This paper presents a promising technology to make quantum-well InAs transistors on SiO2/Si substrate by using a self-aligned gate-last fabrication technique. The full self-aligned fabrication process is demonstrated, and the fabricated device is characterized. A 2-D TCAD simulation is then performed based on the experimental data to understand the operation of the InAs transistors. We explore further optimizations for this technology through TCAD simulations, and it is found that with optimizations in materials, device geometry and fabrication, significant boost in RF performances is possible with these devices.

Scalability and Stability Enhancement in Self-Aligned Top-Gate Indium- Zinc-Oxide TFTs With Al Reacted Source/Drain

A self-aligned fabrication process for top-gate amorphous indium–zinc–oxide (a-IZO) thin-film transistors (TFTs) is demonstrated. Aluminum (Al) thermal treatment is employed to dope the a-IZO layer and thus form the self-aligned source/drain regions. The results show that the sheet resistance of the Al-treated a-IZO layer can be as low as 360 $\Omega / \Box $ . The fabricated top-gate TFTs typically have a mobility of 16.84 cm2/V $\cdot $ s, subthreshold swing of 0.14 V/dec and on/off current ratio of > 109. The Al-treated TFTs show a significant scalability and stability enhancement compared to the conventional Ar plasma-treated ones. This enhancement can be attributed to the thin Al2O3 layer formed on source-drain area that blocks the diffusion of hydrogen or H2O from the passivation layer into the source-drain and channel regions.

Electrical and Structural Characterization of Self-Aligned InGaZnO Thin-film Transistors Fabricated by Excimer Laser Irradiation

We conducted electrical and structural characterization of a self-aligned InGaZnO (IGZO) thin-film transistor (TFT) fabricated by selectively reducing the resistance of the source and drain (S/D) regions by backside excimer laser irradiation. We present the influence of the resistance of the S/D regions on the transfer characteristics and discuss the applicability of our resistance reduction method to the self-aligned oxide TFT fabrication process. In our proposed method, since the low-resistance regions are formed directly by using the gate electrode as a mask, the positions of the S/D regions can be accurately set. We demonstrate this by analyzing the spreading resistance and height profiles for the IGZO film.

A niobium oxide-tantalum oxide selector-memristor self-aligned nanostack

The integration of nonlinear current-voltage selectors and bi-stable memristors is a paramount step for reliable operation of crossbar arrays. In this paper, the self-aligned assembly of a single nanometer-scale device that contains both a selector and a memristor is presented. The two components (i.e., selector and memristor) are vertically assembled via a self-aligned fabrication process combined with electroforming. In designing the device, niobium oxide and tantalum oxide are chosen as materials for selector and memristor, respectively. The formation of niobium oxide is visualized by exploiting the self-limiting reaction between niobium and tantalum oxide; crystalline niobium (di)oxide forms at the interface between metallic niobium and tantalum oxide via electrothermal heating, resulting in a niobium oxide selector self-aligned to a tantalum oxide memristor. A steady-state finite element analysis is used to assess the electrothermal heating expected to occur in the device. Current-voltage measurements and structural/chemical analyses conducted for the virgin device, the electroforming process, and the functional selector-memristor device are presented. The demonstration of a self-aligned, monolithically integrated selector-memristor device would pave a practical pathway to various circuits based on memristors attainable at manufacturing scales.

Single lithography-step self-aligned fabrication process for Vertical-Cavity Surface-Emitting Lasers

We demonstrate a self-aligned process to fabricate Vertical-Cavity Surface-Emitting Lasers (VCSEL) which combines, within a single lithographic step the mesa etch, the surface passivation, the opening of the emission window and the top annular metallization. This process flow, based on a double photoresist layer enabling two lift-off steps, offers great advantages such as easy and fast implementation while insuring a perfect alignment between the emitting window, the passivation layer aperture and the metal-ring contact. VCSEL fabrication is drastically simplified and its repeatability improved. Finally, this process can be advantageously applied to other photonic devices such waveguide-ridge lasers, modulators, LED, etc.

ECF micropump fabricated by electroforming with novel self-aligned micro-molding technology

This paper proposes and presents a novel ECF (electro-conjugate fluid) micropump with TPSEs (triangular prism and slit electrode pair) fabricated by electroforming process using newly developed self-aligned micro molds. ECF is a kind of functional and dielectric fluid. ECF micropump is based on the principle of ECF jet, which is a powerful and active jet flow generated between electrodes immerged in ECF, when high DC voltage is applied to the electrodes. Our previous research experimentally demontrated that the ECF micropump had high power density thanks to the 2D-integraton (serialized integration and paralleled integration) of our proposed MEMS fabrication method by using micro-molding and electroplating. Moreover, it was also proved that higher aspect ratio of TPSEs by the multilayer fabrication process resulted in higher flow rate of the ECF micropump. However, the multilayer fabrication has demerit to require precise alignment that is time-consuming and extremely difficult to be met. In order to improve alignment accuracy and alleviate fabrication difficulty, this paper proposes a novel self-aligned MEMS fabrication process for high aspect ratio TPSEs. The ECF micropump by this newly-proposed MEMS process was successfully fabricated and the feasibility was proved by experimentally investigating output performance of the ECF micropump.

Single mask fabrication process for movable MEMS devices

The current work reports on the realization of movable micromachining devices using self-aligned single-mask fabrication process. Only dry etching process utilizing inductively coupled plasma reactive ion etching was used to release 3D micro structures from single crystal silicon substrate. No wet etching process is required to release the structures as is the case with silicon on insulator (SOI) wafers. Also the developed process does not require an SOI substrate and accordingly dispensing with the application of a wet etching step, thus yielding uniform structures without stiction. The optimized process was applied to realize thermally actuated microgrippers. The article presents the development of the fabrication process and demonstrates the operation of the fabricated device. The optimized process provides an avenue for low cost fabrication of movable micromachining devices without the use of complicated wet etching steps typically associated with SOI substrates.

Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure

A vertical silicon-on-insulator (VSOI)-based capacitorless 1T-DRAM cell with a trench body structure is proposed. The trench body is added as an additional neutral region under the device channel region through a self-aligned fabrication process in a 300 nm wide VSOI MOSFET that enables the device to separate the hole storage region and sense electron current region without extra area penalty. With the holes stored in the trench body, the floating-body effect occurs and affects the threshold voltage significantly. A Synopsys TCAD software tool is also used to evaluate the device performance for DC and transient analysis. The electrical and transient characteristics confirm how the proposed device with trench body can be used perfectly as a 1T-DRAM application to achieve desirable performance in terms of a larger programming window and longer retention time.

Design and Fabrication of Carbon Nanotube Field‐Emission Cathode with Coaxial Gate and Ballast Resistor

A low density vertically aligned carbon nanotube-based field-emission cathode with a ballast resistor and coaxial gate is designed and fabricated. The ballast resistor can overcome the non-uniformity of the local field-enhancement factor at the emitter apex. The self-aligned fabrication process of the coaxial gate can avoid the effects of emitter tip misalignment and height non-uniformity.

SPICE Modeling of the Scaling of Resonant Tunneling Diodes and the Effects of Sidewall Leakage

Si/SiGe and AlGaAs/GaAs resonant tunneling diodes (RTDs) are realized using a self-aligned fabrication process with dimensions ranging from 50 μm down to 30 nm. Using these devices, scaling rules are developed and incorporated into a modified SPICE model. The depletion width and the sidewall current are extracted from the model. The results confirm that the parasitic sidewall current is responsible for the reduction in peak-to-valley current ratio (PVCR) in small-diameter RTDs. A new device layout is demonstrated to significantly reduce the sidewall current for optimum nanoscale performance. Improvements in the PVCRs are demonstrated by this approach.