Abstract

A vertical silicon-on-insulator (VSOI)-based capacitorless 1T-DRAM cell with a trench body structure is proposed. The trench body is added as an additional neutral region under the device channel region through a self-aligned fabrication process in a 300 nm wide VSOI MOSFET that enables the device to separate the hole storage region and sense electron current region without extra area penalty. With the holes stored in the trench body, the floating-body effect occurs and affects the threshold voltage significantly. A Synopsys TCAD software tool is also used to evaluate the device performance for DC and transient analysis. The electrical and transient characteristics confirm how the proposed device with trench body can be used perfectly as a 1T-DRAM application to achieve desirable performance in terms of a larger programming window and longer retention time.

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