Abstract
Si/SiGe and AlGaAs/GaAs resonant tunneling diodes (RTDs) are realized using a self-aligned fabrication process with dimensions ranging from 50 μm down to 30 nm. Using these devices, scaling rules are developed and incorporated into a modified SPICE model. The depletion width and the sidewall current are extracted from the model. The results confirm that the parasitic sidewall current is responsible for the reduction in peak-to-valley current ratio (PVCR) in small-diameter RTDs. A new device layout is demonstrated to significantly reduce the sidewall current for optimum nanoscale performance. Improvements in the PVCRs are demonstrated by this approach.
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