Self-aligned Double Patterning Research Articles

Understanding Growth Mechanism of Atomic Layer Deposition of Tisiox for Spacer in Double Patterning Process

The aggressive scaling down of patterning technology in semiconductor industry is challenging owing to the limitation of current extreme ultraviolet EUV lithography technique, thus applying self-aligned double patterning (SADP) is essential. In this regard, TiSiOx may be a promising spacer material for SADP, which is beneficial to tolerate high aspect ratio structure triggered by shrinkage in patterning size. However, atomic layer deposition (ALD) of quaternary materials is usually faced to unexpected growth characteristics leading to undesired film qualities, while precise control of thickness and film properties is vital to achieve SADP. This work provide understanding of how growth characteristics of ALD TiSiOx are deviated according to process temperature. At 100 °C, hygroscopic TiSiOx surface which is originated by the presence of Ti-O-Si bond is exposed to H2O by-product leading to enhanced growth rate of TiSiOx compared to ideal case. If the process temperature is increased to 200 °C, opposite behavior is observed since hygroscopic TiSiOx surface characteristic is no more dominant to growth rate of ALD TiSiOx due to dehydroxylation. Theses nonconventional growth characteristics dramatically influence on hydroxyl concentration in TiSiOx films resulting in different spacer qualities such as dry etch rate and elastic modulus. These correlative results suggest that the process conditions should be modulated to suppress hydroxyls incorporation into growing TiSiOx surface during ALD to obtain a high-quality TiSiOx thin films for SADP.

Source and drain formation in FinFETs

This paper talks about the background and motivation of fin field-effect transistors (FinFETs) to address the short-channel effect and improve the performance of transistors. Also, this paper focuses on the manufacturing formation of source and drain in FinFETs, which is Self-Aligned Double Patterning (SADP) and discusses the challenges faced in fabrication and design, including self-heating effect and body punch-through in FinFET devices. Furthermore, this paper mentions the prospects of vision and design technology. The insight gained from this paper can enhance understanding of some parts of the manufacturing process in FinFETs and help improve fabrication technology.

Process optimization for shallow trench isolation etch using computational models

The critical dimensions of advanced semiconductor manufacturing processes have decreased to a few tens of nanometers while the aspect ratios have increased beyond 100. The performance of plasma etch patterning processes as well as the cost and time of the development cycle are critical to the success of ramping a new technology node toward profitable high-volume manufacturing. In this paper, a computational patterning software, ProETCH®, has been developed with rigorous physics and advanced algorithms for modeling the etch patterning process, with the featured capabilities in calibrating the reaction mechanisms and optimizing the etch process. A shallow trench isolation etch process using self-aligned double patterning was investigated. A reaction mechanism of silicon etch by Ar/Cl2 plasma was developed to address the surface reactions, and a plasma hypermodel was introduced to correlate process operating conditions to plasma parameters at the wafer surface. The parameters of the reaction mechanism and the plasma hypermodel were calibrated with experimental data obtained from cross-sectional scanning electron microscope (XSEM) images. The calibrated model is used to identify the different fundamental pathways that contribute to the observed profile metrics in XSEMs. The model was then used for process development and optimization by solving the forward and inverse problems. In the forward problem, the model is used to predict the etching profile at different process conditions. Predictions for both interpolation conditions (process parameters within the range used for developing the model) and extrapolation conditions (process parameters outside of the range used for developing the model) agree well with the experimental data with the root mean square error less than 4 nm (1 nm resolution used for the mesh). In the inverse problem, the developed model is used to search for process conditions (e.g., values of bias power and pressure), which could result in desirable profiles. The solutions to the inverse problem demonstrate a degeneracy in process space of the etching process for a given target profile.

B-open Defect: A Novel Defect Model in FinFET Technology

This article proposes an electrical analysis of a new defect mechanism, to be named as b-open defect, which may occur in nanometer technologies due to the use of the Self-Aligned Double Patterning (SADP) technique. In metal lines making use of the SADP technique, a single dust particle may cause the simultaneous occurrence of a bridge defect and an open defect. When the two defects impact the same gates, the electrical effects of the bridge and the open combine and exhibit a new specific electrical behavior; we call this new defect behavior a b-open. As a consequence, existing test generation methodologies may miss defect detection. The electrical behavior of the b-open defect is first analyzed graphically and then validated through extensive SPICE simulations. The test pattern conditions to detect the b-open defect are finally determined, and it is shown that the b-open defect requires specific test generation.

Process window improvement for fin cut layer in self-aligned double-patterning process based on backscattered electron imaging

BackgroundThe self-aligned double-patterning (SADP) process is being used extensively to overcome the lithographic resolution limit in the manufacture of integrated circuits. One use case is fin definition in a fin field-effect transistor. Fin cut layers are applied to modify the fins to the requirements of the device designs.AimThe traditional secondary electron (SE) imaging exhibits a disadvantage in the process controlling the fin cut layers, and fin damage defects were observed. This work aims to improve the monitoring and controlling capabilities for the process quality of fin cut layers.ApproachA specially designed fin cut process flow and a backscattered electron (BSE) imaging technique are applied to check the process quality. The patterns formed through the fin cut etch and the fin structures are identified and measured simultaneously in one BSE image.ResultsBy measuring the edge-to-edge distance, pitch walking (PW) of fins, and overlay (OV), the root cause of the fin damage is revealed. The linear fitting model and third-order fitting model are applied to reduce the edge placement error (EPE). The edge distance protecting the “at risk” fin is enlarged from 5.6 to 11.6 nm. The range of the distance is reduced from 11.6 to 8.1 nm, and the improvement in standard deviation is about 33%.ConclusionsThis work shows the capability of the BSE imaging technique in the characterization of fin cut layers and the potential in process window improvement restricted to fin damage defects.

Bottom grating asymmetry-induced inaccuracy in diffraction-based overlay measurement

Background: Overlay (OV) is a very important indicator for characterizing the pattern position accuracy between two layers in an integrated circuit in the manufacturing industry. The self-aligned double-patterning (SADP) process, which is limited to the resolution of deep ultraviolet lithography, is being extensively used for the volume manufacturing of integrated circuits. However, compared to the planar process, the SADP process poses new challenges for OV control.Aim: We investigate the bottom grating asymmetry of a microdiffraction-based overlay (μDBO) target in the SADP process and its effect on OV measurement.Approach: The bottom grating of the OV metrology target is analyzed through scanning electron microscopy and transmission electron microscopy. The imbalance of the −1st- and +1st-order diffraction light intensities of the asymmetrical bottom OV target is characterized. Finally, the effects of light polarization and wavelength on the OV accuracy are simulated.Results: Asymmetric behavior of bottom OV grating is identified. OV dependency on the measurement-light polarization is determined. The simulation results indicate that wavelength and polarization affect the OV accuracy simultaneously.Conclusions: We studied the bottom grating asymmetry-induced inaccuracy in DBO measurement and can assist in understanding the mechanism of measurement light-interaction with the OV grating to enhance the DBO accuracy to a new level.

High density hexagonal MTJ array with 72 nm pitch and 30 nm CD by using advanced DRAM patterning solution and ion beam etch

A hexagonal honeycomb magnetic tunneling junction array with 72 nm pitch and 30 nm MgO critical dimension was successfully fabricated on a 1× nm dynamic random access memory platform by using a mature dynamic random access memory patterning solution and ion beam etch. To our knowledge, both pitch size and critical dimension size are the world’s smallest ones for industrial magnetic tunneling junction arrays. To obtain such a high density and small sized magnetic tunneling junction array, a cross self-aligned double patterning technique, a triple layer hard mask scheme, and an optimized ion beam etch condition were adopted. During the optimization of the ion beam etch process, the dependence of a magnetic tunneling junction pillar profile on ion beam etch parameters for a high density hexagonal magnetic tunneling junction array has also been systematically studied. The depth of oxide recess and the magnetic tunneling junction sidewall angle increased with the ion beam etch amount, while magnetic tunneling junction critical dimension and hard mask remainder thickness decreased with increasing ion beam etch amount.

In-depth feasibility study of extreme ultraviolet damascene extension: Patterning, dielectric etch, and metallization

While semiconductor logic device nodes keep moving to N3 and beyond, the backend of line (BEOL) metal pitch is aggressively scaling to improve device performance and density. BEOL damascene extension refers to interconnect with a full metal pitch of 26–21 nm. The challenges of damascene extensions are profoundly critical due to an extreme ultraviolet (EUV) single exposure limit, dielectric etch, and metallization challenges. Multipatterning is required as well as more advanced low K dielectric etch. Severe line wiggling, bad via/contact hole open, and via/trench short issue can easily be observed. Cu resistance also contributes to most of the device’s R/C delay. Before transitioning to subtractive metal integrations, there is no doubt that multipatterning damascene extension plays an important role in bridging the gap between them. In this work, we provide an in-depth feasibility study on damascene extension focusing on EUV self-aligned double patterning with cut and block assembly for 24 nm pitch line and space. EUV double patterned self-aligned via is also validated for the dual damascene test. Both continuous wave and quasiatomic layer etch are developed to achieve a wiggling-free, bridge-free, and high metal hard mask selectivity process in TEL’s new generation capacitively coupled plasma etchers. Copper metallization is demonstrated in both via and trench of a 24 nm pitch. This report provides an important insight into damascene extension feasibility for high volume manufacturing.

72 nm Pitch Hexagonal MTJ Array on DRAM Platform for High-Density MRAM

Well isolated 72 nm pitch hexagonal honeycomb magnetic tunneling junction (MTJ) array with about 45 nm MgO CD was successfully fabricated on a DRAM platform by using mature DRAM array patterning solution with self-aligned double patterning technology and proposed triple hard mask scheme. The 72 nm pitch MTJ array had an equivalent cell size as small as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.0044~\mu \text{m}$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the world’s smallest pitch size and cell size for industrial MTJ array to our knowledge. The hexagonal array geometry offered considerably merit for storage density enhancement and MTJ etch convenience. A reactive ion etch (RIE) and ion beam etch (IBE) combined MTJ etching solution was adopted to optimize pillar isolation and mitigate metallic re-deposition and etch damage. Perpendicular magnetic anisotropy was maintained in MTJ array; however, free layer coercivity was smaller than expected, indicating the existence of etch damage or fringe magnetic field interaction. Potential challenges for the chip integration of high-density hexagonal MTJ array are also discussed.

Line edge roughness reduction for EUV self-aligned double patterning by surface modification on spin-on-carbon and tone inversion technique

Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER). In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects, which can lead to device degradation by defect formation and edge placement error (EPE). LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our study, we examine a technique to reduce LER on the EUV SADP line pattern. This technique involves the surface modification on the spin-on carbon (SOC) layer in the patterning stack and tone inversion process. We had found a trend between surface hydrophobicity of the SOC and the EUV SADP LER performance. The condition that increased the hydrophobicity of the SOC resulted in a lower LER performance after tone inversion. The tested conditions include direct current superposition (DCS) function with H2 plasma, fluorocarbon plasma, and the combination of DCS with H2 plasma and trimethylsilane dimethylamine deposition. On 20-nm pitch EUV SADP, this technique shows 26% of LER improvement from lithography to SADP formation. PSD analysis recorded about 6% and 30% of the LER improvement at the correlation length of >200 nm and 200 to 30 nm, respectively. A demonstration of this technique for a further scaling to 15-nm pitch also shows an LER reduction of 30% from lithography to SADP formation.

A novel self-aligned double patterning integrated with Ga+ focused ion beam milling for silicon nanowire definition

Self-aligned double (SADP) or quadruple (SAQP) patternings have been used to obtain sub-resolution lithographies (sub-10 nm). For this purpose, usually, these patternings are integrated with 193 nm immersion (193iL), extreme ultra-violet (EUVL) and electron beam (EBL) lithographies. In this work, SADPs are integrated with Ga+ Focused Ion Beam (FIB) milling, which is a novel alternative to traditional 193iL, EUVL and EBL, mainly for prototyping of nanodevices. Furthermore, the FIB milling is a maskless process, thus being more flexible than EBL and cheaper than EUVL. The FIB milling was carried out on the a-Si:H/Al (deposited on Si substrate) to pattern the parallel Al nanowires (AlNWs), which are used as mandrel in our SADP. The a-Si:H layer, used as spacer in our SADP, also is an effective barrier against the Ga+ ion bombardment directly on Al surface, avoiding damages on the AlNW mandrel. Thus, after FIB milling, SADP and plasma etch steps, Silicon Nano-Wires (SiNWs), with dimensions (extracted by Scaning Electron Microscopy (SEM)) of fin width and pitch of 35 nm and 170 nm, respectively, were obtained. This is an excellent result, similar to obtained by SADP methods integrated with traditional lithographies. Therefore, our SADP with FIB milling is a flexible alternative to obtain SiNWs for 3D nanostructure technologies prototypes. Furthermore, a last important result, extracted from energy dispersive x-ray spectroscopy (EDS) spectrum, is the Ga peak absence, indicating that no trace of gallium (for an EDS detection limit of 1%) could be detected into SiNWs. This result agrees the TRIM (Transport and Range of Ions in Matter) simulation of gallium ion implantation in a-Si:H/Al structure.

(Invited) Process Development of CMOS TFTs for Monolithic 3D-IC Applications

Three-dimensional integrated circuit (3D-IC) technology has been used for vertical integration of multi-chip or stacked process in three-dimensional space for the scaling trend of sub-1 nm technical node, in order to overcome the physical limits of electronics and materials in the semiconductor process. Among them, monolithic 3D-IC has many features that can solve the challenge of stacking 2D molds and connecting them in the third dimension. 3D-IC has many significant advantages, such as heterogeneous integration, a smaller footprint but more powerful features, lower costs, reduced power, and higher bandwidth.In this talk, process development of CMOS thin film transistor (TFT) for monolithic 3D-IC will be presented. The channel material of upper layer is the key concern for fabricating device stacked in 3-D space due to the process thermal budget. An amorphous indium gallium zinc oxide (a-IGZO) with activation temperature under 350 ℃ is regarded as the most promising transparent amorphous oxide semiconductor (TAOS) channel material for the advanced TFT device. However, the TAOS TFT is lack of p-channel device. Hence in this work, a top gate poly-Si p-channel TFT (pTFT) device was formed with tri-gate structure by using a self-aligned double patterning (SADP) process. Then, an a-IGZO n-channel TFT (nTFT) based on a bottom gate process were stacked with a monolithic architecture on the same wafer.At first, the process development and optimization of individual AOS nTFT and poly-Si pTFT were carried out. The device structure of AOS nTFT includes a 100 nm-thick TiN metal bottom-gate, 10 nm-thick HfO2 gate dielectric, and IGZO channel. On the other hand, a 100 nm-thick TiN metal top-gate, 10 nm-thick HfO2/ 1 nm-thick SiO2 gate stack, p-type JL poly-Si channel, and tri-gate structure were applied for the poly-Si pTFT. Results show that the on/off current ratio (Ion/Ioff) values of AOS nTFT and poly-Si pTFT are 7 and 6.8 orders, respectively. And the subthreshold swing (S.S.) values are135 and 128 mV/decade, respectively. The device performance of the individual n/p TFTs in this work is similar to that of state-of-the-art devices.Afterwards, hybrid CMOS inverter devices were fabricated and stacked with a monolithic 3D-IC architecture. The Ion/Ioff values of AOS nTFT and poly-Si pTFT are 7.1 and 6.3 orders, respectively. And the S.S. values are135 and 133 mV/decade, respectively. The device performance is quite similar to those of individual n/p TFT fabricated in our group before. Results indicate that the process integration of the AOS nTFT and poly-Si pTFT for monolithic IC is successful. The electrical characteristics of CMOS TFT inverter are pretty good. The voltage gain is ~ 25, the mid voltage is ~ 0.5 Vdd, and the high/low noise margins are large and approximately equal.In order to further improve the performance of nTFT, a novel tungsten (W) dopant was applied to replace gallium (Ga) for ASO film due to its lower price and higher oxygen bond dissociation energy. With higher oxygen bond dissociation energy, the oxygen vacancy can be well controlled and the device may achieve better electrical and reliability characteristics. It is found that the a-IWZO nTFT shows a ION/IOFF value of 7.8 order and a S.S. value of 109 mV/decade. Furthermore, the mobility of a- IWZO TFT is about 2 times higher than that of a-IGZO TFT. The a-IWZO TFT with tiny W dopant as the carrier suppressor can exhibit a smaller S.S. value, suggesting that the channel can be effectively controlled even with higher channel conductivity.To further improve the performance of pTFT, a polycrystalline germanium (poly-Ge) junctionless (JL) TFT is studied. The implantation and activation processes are not required for poly-Ge JL device because the vacancy and interstitial in poly-Ge film can act as acceptors, which naturally turn the film into p-type. However, Ge with poor thermal stability is very sensitive to process temperature. The Ge sub-oxides at Ge surface have lower bandgap, more oxide traps, and interface states, and they may diffuse into gate dielectric after thermal process, resulting in degradation of gate dielectric. The desorption and diffusion of GeOx can be suppressed by nitridation process on interfacial layer (IL) at high-k/Ge. Therefore, in this work, poly-Ge JL pTFT devices with various ILs including GeO2, GeON, O2 plasma-treated HfN, and O2 plasma-treated Al2O3 HfO2 are investigated and compared. The optimal IL for poly-Ge pTFT could be expected. Then, a CMOS device by integrating AOS nTFT and poly-Ge pTFT with a monolithic architecture will be performed as well.

Integrated in situ self-aligned double patterning process with fluorocarbon as spacer layer

Self-aligned double patterning (SADP), or spacer lithography, is a widely used technique in the semiconductor industry for high-throughput nanoscale pattern definition and thus is of great significance for very-large-scale integration, large-area photonic device fabrications, and other applications. In a standard SADP flow, chemical vapor deposition or atomic layer deposition is used to deposit a conformal spacer layer, which is typically a dielectric material. The spacer composition and film quality will influence downstream critical dimension control. However, samples have to go through multiple processing environments, and fabrication complexity is thus increased. In this work, an in situ SADP process is proposed, with all the fabrication steps being integrated into a single process inside a commercially available plasma etching equipment. The spacer layer is a plasma-deposited fluorocarbon film, which has a uniform step coverage and a good etch selectivity to silicon. Various nanostructures have been fabricated to prove the capability of this technique. With its high integrity and technical convenience, this method can be promising to improve the throughput and efficiency of nanofabrication in the semiconductor industry, microelectromechanical systems, and photonic engineering.

Self-aligned double patterning for active trim contacts with anisotropic pattern pitches in sub-20 nm dynamic random access memories

Background: With continuous decrease in the technology node of dynamic random access memories (DRAMs) down to sub-20 nm, the self-aligned double patterning (SADP) is an effective approach to generate two-dimensional (2-D) patterns, particularly contact arrays. Aim: We demonstrate a patterning scheme using the SADP technique to produce active trim contacts with anisotropic pattern pitches. Approach: The proposed scheme uses two consecutive spacer-formation processes. Results: By making the ellipsoidal core pillars and minimizing the spacer thickness, 2-D critical dimensions (CDs) for self-generated contacts match well with those for core contacts. In addition, an interesting cross-dependence of X -CD and Y -CD variations for the core and self-generated contacts is observed. Conclusion: This patterning approach is useful for forming active trim contacts in sub-20 nm DRAMs using fewer numbers of ArF immersion photolithography steps.

Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning

Redundant via (RV) insertion helps prevent via defects and hence leads to yield enhancement. However, RV insertion in self-aligned double patterning (SADP) processes is challenging since cut optimization has to be considered together. In SADP, parallel one-dimensional metal lines are divided into signal wires and dummy wires by line-end cuts. If an RV is inserted, signal wires need to be extended to connect to the RV. To this end, an additional cut, which we call RV cut, is introduced to make a space for the extension. Since RV cuts and line-end cuts are manufactured with the same mask set, design rules between those cuts have to be honored, which incurs proper distribution and mask assignment to individual cuts. In this article, we address a problem of integrated RV insertion and cut optimization. We show that the problem can be formulated as an integer linear programming (ILP). We also propose a heuristic algorithm is presented for practical application, in which potential locations of RVs are first identified and used to properly insert as many RVs as possible while minimizing the conflict between RV cuts. Our experimental results demonstrate that 75% of vias receive RVs with 8% increase in total wire length, which is only slightly worse than the optimal result obtained by ILP.

(Invited) Towards Selective Etching with Nanometric Control Using Remote Plasma Source

The transition from planar Metal-Oxide-Semiconductor (MOS) transistor architecture to 3 Dimension (3D) Field Electron Transistor (FET) architecture has been necessary to pursue transistor scaling and overcome high power consumption of logic chip. Today, the Fin Field Electron Transistor (FinFET) structure is used in the most advanced (16-/14-nm generation) CMOS technologies.[1] To continue device scaling at least to the 5nm technology node, new 3D designs, such as GAA FEt are anticipated to be adopted in the future CMOS technology generations in order to provide for superior electrostatic integrity.[2] 3D MOS architectures bring their own set of challenges for etch applications. While planar devices relied more on anisotropic etching, 3D devices require more isotropic etch capabilities with high selectivity between different materials and a nanometric precision of the etching. This work proposes a new route to achieve selective etching using a prototype of reactor combining in the same chamber a remote plasma source (RPS) and a capacitively coupled plasma (CCP) source. The proposed approach relies on cycling a two-step process comprising a functionalization step and a selective removal step of the functionalized surface over the non-functionalized one. If isotropic selective etching is needed, the chemical and isotropic action of the radicals produced in the remote plasma is used to selectively functionalize the material surfaces. On the other side, if topographically-selective etching is needed, the horizontal surfaces are selectively functionalized over vertical surfaces by using implantation of ions produced by the CCP source. The subsequent removal step uses the high selective capability of remote plasma processes (cf. Figure 1). The cycling of those two steps allows the nanometric control of the etching. The concept is inspired by what is already done in the field of atomic layer deposition (ALD) to make selective deposition. [3] [4] The current trend in ALD is to chemically and locally bond a molecule directly to the surface in order to inhibit reactive sites and then prevent further reactions between the ALD precursor molecules. By selectively functionalizing the surface of the materials in presence, selective deposition can be obtained. In our case, it happens that remote plasma processes whose etching mechanisms rely on the action of chemical plasma neutrals are very sensitive to the chemistry of the substrate. By modifying the material surface state with a treatment, the etching can be delayed or even suppressed, converting a non-selective surface into one for which the etching process is area selective. The concept is validated in two case studies. First, it is developed to achieve the isotropic and selective removal of SiGe relative to Si layers in order to fabricate horizontal stacked-Si nanowires for Gate All Around devices. For this particular application, the two-step process is composed of an oxidation step using remote He/O2 remote plasma and an etching step using remote NH3/NF3/O2 remote plasma. It is shown that the Si oxidation during the first step delay or even suppress the Si etching in NH3/NF3/O2 plasma during the second step, allowing very high SiGe over Si selectivity (>60). Secondly, it is applied to the topographically-selective Nitride spacer etching. In this case, the horizontal nitride surfaces were functionalized by H2 ion implantation and the removal step used NH3/NF3/He remote plasma process. Indeed, while pristine SiN is not etched in NH3/NF3/He remote plasma, it is shown that the H implantation has a catalyzing effect on the etching, allowing the removal of horizontal SiN surface with almost infinite selectivity over vertical surface. This work shows that the concept that we propose is very promising for the development of highly area selective etching processes. This work was financially supported by the LabEx Minos ANR-10-LABX-55-01 and the French RENATECH network and technically supported by AMAT France and AMAT USA [1] S. Natarajan et al., “A 14 nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm2 SRAM cell size,” in IEDM Tech. Dig., pp. 3.7.1–3.7.3 (2014). [2] P. Zheng, D. Connelly, F. Ding, and T.-J. King Liu, IEEE Trans. Elec. Dev., 62, NO. 12, 3945 (2015) [3] F. S. Minaye Hashemi, B. R. Birchansky, and S. F. Bent, “Selective Deposition of Dielectrics: Limits and Advantages of Alkanethiol Blocking Agents on Metal−Dielectric Patterns” Appl. Mater. Interfaces 2016, 8, 33264−33272 [4] W-H Kim, F. Sadat Minaye Hashemi, A. J. M. Mackus, J. Singh, Y. Kim, D Bobb-Semple, Y. Fan, T. Kaufman-Osborn, L. Godet, and S. F. Bent, A Process for Topographically Selective Deposition on 3D Nanostructures by Ion Implantation ACS Nano 2016, 10, 4451−4458 Figure 1

Combining double patterning with self-assembled block copolymer lamellae to fabricate 10.5 nm full-pitch line/space patterns

Directed self-assembly of block copolymers and self-aligned double patterning are two commonly used pitch scaling techniques to increase the density of lithographic features. In this work, both of these pitch scaling techniques were combined, enabling patterning at even higher densities. In this process, directed self-assembly of a high-χ block copolymer was used to form a line/space pattern, which served as a template for mandrels. Via these mandrels, atomic layer deposition was used to deposit a thin aluminium oxide spacer. By this method, a total pitch scaling factor of 8, equivalent to a 10.5 nm full pitch, was reached. The types of defects and the line roughness at the different steps of the process were discussed.

Self-aligned blocking integration demonstration for critical sub-30-nm pitch Mx level patterning with EUV self-aligned double patterning

We report a sub-30-nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology targeting the back end of line metal line patterning applications for logic nodes beyond 5 nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193-nm immersion SADP targeting a 40-nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, spin on carbon, spin on glass). The multicolor integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and, more generally, edge placement error as a whole for advanced process nodes. Unbiased line edge roughness (LER)/line width roughness (LWR) analysis comparison between EUV SADP and 193-nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open, and dielectric etch compared to 193-nm immersion SADP, the final process performance is matched in terms of LWR (1.08-nm 3 sigma unbiased) and is 6% higher than 193-nm immersion SADP for average unbiased LER. Using EUV, SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.

Improvement of Line Width Roughness and Line Edge Roughness for Ultrascaled Finfet Technologies

As FinFET feature size scaling down, the fins are against more critical challenges by using either self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) method. Wiggling, line width roughness (LWR) and line edge roughness (LER) play more crucial roles at sub-14nm technology and beyond. Traditionally, post plasma treatment methods for photoresist are largely investigated to improve the LWR and LER. For the SADP and SAQP technology, pattern transferring is also another critical feature of dry etch process for pattern line wiggling. In this paper, both plasma photoresist treatment and dry etch process optimization are studied for improving LWR and LER.

Etch considerations for directed self-assembly patterning using capacitively coupled plasma

Alternative patterning strategies are pursued to push the device feature size below the physical limit of optical lithography as the semiconductor manufacturing industry is preparing for production at sub-10 nm technology node. Extreme ultraviolet (EUV) lithography, 193 nm immersion augmented with multiple patterning schemes (“self-aligned double patterning,” “self-aligned quadruple patterning”) and “directed self-assembly (DSA)” are being evaluated as alternatives to meet rising demands of aggressive patterning. EUV lithography reduces the number of processing steps, but it is yet to achieve full maturity in terms of resist materials, throughput, and manufacturability. DSA when augmented with 193 nm immersion guide prepatterns can aid in reducing the pitch of final structures. There is no infrastructure upgrade cost involved as the key processing steps of DSA are conducted in existing wafer track systems. The authors have successfully demonstrated DSA pattern transfer into metal hard masks for the back end of the line application and nonmetal hard masks for the front end of the line applications. However, DSA comes with its own challenges posed in the form of polymer-to-polymer selectivity, mask budget, post-lithography defects, mask shape, critical dimension control, and line edge roughness (LER). The authors address the challenge of selectivity and roughness correction by using spatially uniform low-density plasma obtained in dual (low and high) frequency midgap capacitively coupled plasma etcher. A parametric study of an O2/Ar gas chemistry based plasma etch of widely studied poly(styrene-block-methyl methacrylate) (PS-b-PMMA) films is used to describe how plasma parameters impact PMMA removal selective to PS and LER during plasma etch pattern transfer using DSA lithography. The effects of etchant gas concentration and deposition gas addition for preferential passivation of the PS mask are investigated during PMMA etch. Their results indicate modulation of ion energy through bias power adjustments can be used to improve selectivity. Zero bias power optimal; however, roughness degrades at this condition necessitating inclusion of other solutions. Controlled addition of hydrocarbon gas enhances the selectivity further. Low frequency peak-to-peak voltage and high frequency power most strongly correlate with LER; hydrocarbon addition has little effect. Relative balance between various fluxes and ion energy is needed to obtain the maximum reduction in roughness with the required selectivity.