Self-aligned Double Patterning Process Research Articles

Bottom grating asymmetry-induced inaccuracy in diffraction-based overlay measurement

Background: Overlay (OV) is a very important indicator for characterizing the pattern position accuracy between two layers in an integrated circuit in the manufacturing industry. The self-aligned double-patterning (SADP) process, which is limited to the resolution of deep ultraviolet lithography, is being extensively used for the volume manufacturing of integrated circuits. However, compared to the planar process, the SADP process poses new challenges for OV control.Aim: We investigate the bottom grating asymmetry of a microdiffraction-based overlay (μDBO) target in the SADP process and its effect on OV measurement.Approach: The bottom grating of the OV metrology target is analyzed through scanning electron microscopy and transmission electron microscopy. The imbalance of the −1st- and +1st-order diffraction light intensities of the asymmetrical bottom OV target is characterized. Finally, the effects of light polarization and wavelength on the OV accuracy are simulated.Results: Asymmetric behavior of bottom OV grating is identified. OV dependency on the measurement-light polarization is determined. The simulation results indicate that wavelength and polarization affect the OV accuracy simultaneously.Conclusions: We studied the bottom grating asymmetry-induced inaccuracy in DBO measurement and can assist in understanding the mechanism of measurement light-interaction with the OV grating to enhance the DBO accuracy to a new level.

Quasi-bound states in the continuum for deep subwavelength structural information retrieval for DUV nano-optical polarizers.

We demonstrate the retrieval of deep subwavelength structural information in nano-optical polarizers by scatterometry of quasi-bound states in the continuum (quasi-BICs). To this end, we investigate titanium dioxide wire grid polarizers for application wavelengths in the deep ultraviolet (DUV) spectral range fabricated with a self-aligned double-patterning process. In contrast to the time-consuming and elaborate measurement techniques like scanning electron microscopy, asymmetry induced quasi-BICs occurring in the near ultraviolet and visible spectral range provide an easily accessible and efficient probe mechanism. Thereby, dimensional parameters are retrieved with uncertainties in the sub-nanometer range. Our results show that BICs are a promising tool for process control in optics and semiconductor technology.

Integrated in situ self-aligned double patterning process with fluorocarbon as spacer layer

Self-aligned double patterning (SADP), or spacer lithography, is a widely used technique in the semiconductor industry for high-throughput nanoscale pattern definition and thus is of great significance for very-large-scale integration, large-area photonic device fabrications, and other applications. In a standard SADP flow, chemical vapor deposition or atomic layer deposition is used to deposit a conformal spacer layer, which is typically a dielectric material. The spacer composition and film quality will influence downstream critical dimension control. However, samples have to go through multiple processing environments, and fabrication complexity is thus increased. In this work, an in situ SADP process is proposed, with all the fabrication steps being integrated into a single process inside a commercially available plasma etching equipment. The spacer layer is a plasma-deposited fluorocarbon film, which has a uniform step coverage and a good etch selectivity to silicon. Various nanostructures have been fabricated to prove the capability of this technique. With its high integrity and technical convenience, this method can be promising to improve the throughput and efficiency of nanofabrication in the semiconductor industry, microelectromechanical systems, and photonic engineering.

Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment

As the technology nodes scale down to sub-22 nm, double patterning lithography has been considered as a practical solution for layout manufacturing. Compared with litho-etch-litho-etch, self-aligned double patterning (SADP) has better overlay control. To have a better SADP layout decomposability of routing patterns, we consider SADP during detailed routing stage. Two major types of SADP processes are considered: 1) spacer-is-dielectric type and 2) spacer-is-metal type. Different from previous works, the idea of color preassignment is adopted for SADP-aware detailed routing. An elegant graph model is proposed to capture both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules in detailed routing. We apply a negotiated congestion based rip-up and reroute scheme to achieve better routability while maintaining SADP design rules. Compared with other state-of-the-art academic works, our approach does not produce any side overlay error and no SADP design rules violation is reported. Meanwhile, a better solution in terms of total wirelength, routability, and runtime is achieved.

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond

In an increasing interconnect resistance era and aggressive metal pitch scaling, the elevating RC delay could significantly shadow the improvements from advanced device architectures and become a severe design issue. This paper will holistically analyze the interplay between transistors and interconnect delay and the variability induced by back-end-ofline (BEOL) process for the 5-nm node. A global sensitivity analysis using Monte Carlo simulation is employed as a powerful tool for understanding the significance of different variation sources and propagating these process uncertainties to circuit performance and parametric yield. For the BEOL integration process, our results show that dielectric κ-value is the most sensitive parameter. Regarding the patterning options, the BEOL process using self-aligned quadruple pattering with positive tone process requires more than a 4× process margin and suffers from 50% parametric yield loss. The required guardband for lithoetch litho-etch becomes as critical as for the self-aligned double patterning process when the overlay control is 6× higher than the critical dimension control. For trench patterning using spacerdefined techniques, a negative tone process is required to achieve a large process window. From a design perspective, the wire length in SoC can be optimized using a disruptive architecture as a vertical FET, which could potentially reduce the average wire length by 11%.

New alignment mark designs in single patterning and self-aligned double patterning

In single patterning, the increase of odd order diffractive power and decrease of even order diffractive power may improve the wafer alignment performance. A Fourier model is given to quantitatively describe the diffractive optical power of grating structures. Four novel alignment mark structures with higher odd order wafer qualities (WQs) have been optimized based on the model. The accuracy of our model has been validated with almost the same results for different alignment marks using our model and rigorous coupled wave analysis (RCWA). Moreover, three dimensions (3D) of alignment mark should be optimized to get higher WQs for self-aligned double patterning (SADP). Our paper proposes a model to simplify the 3D RCWA algorithm where WQs of SADP grating structures could be split into two different one-direction grating structures. The advantage of the equation makes the evaluation of different grating period of SADP mark fast, accurate and simple. The models and structures of all the designed alignment marks will make it easier for engineers to choose the property alignment mark faced with single patterning or SADP process.

Spectral analysis of sidewall roughness during resist-core self-aligned double patterning integration

Double patterning technology has now proved its efficiency to go beyond the standard lithographic printing limits and address the resolution requirements of the sub-20 nm technological node. However, some data are still lacking regarding the characterization of line edge/width roughness (LER/LWR) in such integration. In this work, a detailed spectral analysis of the sidewall roughness evolution during a resist-core self-aligned double patterning (SADP) integration is presented. A 20 nm half-pitch SADP process using photoresist as the core material, and SiO2 deposited by plasma enhanced atomic layer deposition as the spacer material is developed. The LER and LWR have been characterized at each technological step involved in the SADP process flow, using a power spectral density fitting method, which provides a full description of the sidewalls roughness with the estimation of noise-free roughness amplitude (σ), correlation length (ξ), and roughness exponent (α). Results show that the SADP process allows to decrease drastically the LWR and LER amplitudes down to 2.0 nm corresponding to a reduction of about 70% and 50%, respectively, compared to the initial resist patterns. Although the SADP concept generates two asymmetric populations of lines, the final features present similar LWR, LERleft, and LERright parameters. The study also highlights the effectiveness of the SADP concept to decrease critical dimension variation and low-frequency LWR components to values inferior to 1 nm, which is an outstanding improvement compared to other single or double patterning techniques. However, this work brings out that the deposition process is the key step to ensure successful resist-core SADP integration. It must not only be as conformal as possible but also preserve the square shape of the core material. It is shown that the resist lateral erosion occurring during the deposition step introduces some random resist sidewalls angles that contribute to the formation of short range roughness during the spacer etching transfer, resulting in residual LWR mainly composed of high-and medium-frequency components. Contrary to LWR, the beneficial impact of the conformal spacer deposition on low-frequency roughness components has rather no effect on LER. The LER parameters after spacer etching mainly depend on the core ones prior to deposition. LER low-frequency components remain a key issue to address for an optimized integration.

Self-aligned double patterning process for subtractive Ge fin fabrication at 45-nm pitch

The self-aligned double patterning scheme has been developed for subtractive Ge fin patterning targeting critical dimension (CD) <14nm at pitch of 45nm. Compared to the Si self-aligned double patterning route, several modifications have been undertaken in different steps of Ge fin pattering, such as hard mask trimming and main etch. Out of several trimming options, it is the wet trim that has been qualified at the final stage of hard mask CD trimming. It allows meeting CD specifications for all structures and keeping straight lines without wiggling. Finally, the Ge main etch chemistry has been developed, which provides not only a straight fin profile but a flat etching front without depth loading attributed to different density structures.

Line edge roughness frequency analysis during pattern transfer in semiconductor fabrication

Line edge roughness (LER) and line width roughness (LWR) are analyzed based on the frequency domain 3σ LER characterization methodology during pattern transfer in a self-aligned double patterning (SADP) process. The power spectrum of the LER/LWR is divided into three regions: low frequency, middle frequency, and high frequency regions. Three standard deviation numbers are used to characterize the LER/LWR in the three frequency regions. Pattern wiggling is also detected quantitatively during LER/LWR transfer in the SADP process.

Self-aligned double-patterning layout decomposition for two-dimensional random metals for sub-10-nm node design

Self-aligned double patterning (SADP) is popularly in production use for one-dimensional-type dense patterns with good pitch control in NAND Flash memory applications and the fin layer patterning of FinFET devices, but it is still challenging to apply SADP to two-dimensional (2-D) random metal patterns. We describe the SADP layout decomposition methods for complex 2-D layouts. The SADP for complex logic metals consists of a two mask approach using a core (mandrel) mask and a trim mask. This paper describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in the SADP process. Our technique is validated with 22-nm node industrial standard cells and logic designs, which can be applicable to sub-10-nm node design. Experimental results show that our proposed layout decomposition for SADP effectively decomposes many challenging 2-D layouts.

Novel Clean Concept of Advanced Patterning Film (Amorphous Carbon) for Beyond 2xnm Generation Self-Aligned Double-Patterning (SADP) Process

Advanced Patterning Film (APF, Amorphous Carbon) is newly developed hard mask material by APPLY MATERIALS, Inc. for fine pattern definition, especially used in ArF immersion process. However, amorphous carbon is one candidate of core materials of self align double pattering (SADP) process, usually suggested not to use wet clean process after patter definition due to moisture absorption of APF. We successfully demonstrate better amorphous carbon surface clean performance without any film damaged and line edge roughness (LER) improve 18.2% CD variation, 1.1nm in space even-odd bias beyond 28nm generation. APF of APPLY MATERIALS, Inc. is chemical vapor deposition (CVD) amorphous carbon (a-C) which precursors are normally acetylene (C2H2) and propane (C3H6). Traditional post clean SPM chemical consists of sulfuric acid (H2SO4) and hydro peroxide (H2O2). Hydro peroxide will oxidize amorphous carbon into CO or CO2and result in pattern damaged. We surveyed some post clean candidates in semiconductor fabrication common used, as table 1 shows. Only APM and DHF showed miner or no etching rate to amorphous carbon film. APM is first chosen chemical for amorphous carbon core post etching clean. In Figure 1-a, 3nm/side etching polymer is found on a-C sidewall, and Figure 1-b shows that dry etching polymer are totally removed after APM 10 minutes treatment. However, in SADP process, core material should be with higher removal rate than spacer material, which is usually selected by high temperature deposition film to achieve the high selectivity to core material in core removal process.As Figure 2 shows, amorphous carbon with C2H2precursor is porous structure. 10 minutes APM process will induce moisture absorption by porous amorphous carbon film and line twist in following high temperature spacer material deposition, 450C atomic layer deposition silicon nitride, shows as Figure 3-a. Figure 3-b shows worse even-odd spacer bias after SADP spacer defined. Shorter clean process time and high clean efficiency become the keys of a-C core post clean step. Two chemicals A and B, A is higher fluorine concentration contained and B is lower fluorine concentration contained, a-C core post clean efficiency were investigated and both process times are confined within 90 seconds, including rinse and drying steps. Figure 4-a., 4-b. and 4-c show chemical A has better polymer removal capability than chemical B. Line edge roughness (LER) is reduced from 3.03nm to 2.48nm, 18.2% improvement, shows as Figure 5. In Figure 6 good LER and even-odd space performance of SADP gate definition after adopting chemical A for a-C post etching clean. Long time clean process will result in water absorption of amorphous carbon film due to its porous structure, and will cause worse line edge roughness (LER) in the following high temperature spacer material deposition process. Shorten clean process time to avoid water absorption and improve clean efficiency are the major criteria to achieve successful amorphous carbon clean. Novel a-C clean method by raising F concentration to achieve higher clean efficiency and successfully improve LER 18.2% after core etching and post clean in positive tone SADP process beyond 2xnm generation.

SaDP Process Challenges and Solutions on NAND Flash Cell

Self-aligned double patterning (SaDP) technology has been successfully developed for three critical layers (AA, CG and M2) in NAND flash memories with 3X design rule. In SaDP process, the core performance is extremely critical for even/odd performance which will impact the final profile and etch depth. In this paper, we investigated two etch schemes for core etch. Results showed that scheme I, the traditional core etch, is capabable of forming the vertical core without top corner rounding. Howerer, the remained hard mask on the core top narrows down the subsequent spacer etch window which will influences the pattern transfer performance. Scheme II, with the removal of core hard mask during core etch, is proven to be superior from the point of view of pattern transfer. However, it’s challenging to get vertical and the core without sub-trench. After the optimization of the etch process, the core profile can be well controlled. Besides, the line-end cut process is a must item for SaDP process to separate the adjacent twin lines. Line-end cut could be completed after spacer patterning, final patterning or any other subsequent processes. For control gate (CG), cutting in the subsequent processes is a good choice to avoid the line end extension and AA damage.

Identification and Characterization of a Subtle Bump Defect Formed Upon Organic Mandrel in a Self-Aligned Double Patterning Process

Core bump defect is yield killer in terms of causing blocked etch during poly-Si hard mask etching in the spacer-type self-aligned double patterning (SADP) manufacture process flow. By clarifying the characteristics and formation mechanism of the core bump defect occurred on the top of the organic mandrel post room temperature oxide deposition, several strategies, e.g., electron beam illumination, high/low pressure baking and pulsed plasma etch, were explored. Afterward an effective suppression of the core bump adder was developed, resulting in the sorting yield ramping up by 10% at least.

Defect Gallery and Bump Defect Reduction in the Self-Aligned Double Patterning Module

The self-aligned double patterning (SADP) module is a scheme to form 32 nm or 22 nm line structures that extend the useful range of either dry scanner or immersion scanner photolithography tools. Once reliable baseline processes for SADP flow have been developed, defect data collection, understanding, characterization, and reduction become increasingly important. Knowledge on defect characterization and reduction thus obtained reduces tool ramp-up time at manufacturing sites and provides new directions to improve wafer fabrication processes. In this paper, the types of defects in each step of the process to ultimately form 32 nm or 22 nm structures using the SADP flow are discussed, including an in-depth study of the impact of bump defects on the SADP flow, and proposed mechanisms of bump defect formation. Potential solutions involving an improved film deposition process for the SADP process module are also presented.

John Dalton

In single patterning, the increase of odd order diffractive power and decrease of even order diffractive power may improve the wafer alignment performance. A Fourier model is given to quantitatively describe the diffractive optical power of grating structures. Four novel alignment mark structures with higher odd order wafer qualities (WQs) have been optimized based on the model. The accuracy of our model has been validated with almost the same results for different alignment marks using our model and rigorous coupled wave analysis (RCWA). Moreover, three dimensions (3D) of alignment mark should be optimized to get higher WQs for self-aligned double patterning (SADP). Our paper proposes a model to simplify the 3D RCWA algorithm where WQs of SADP grating structures could be split into two different one-direction grating structures. The advantage of the equation makes the evaluation of different grating period of SADP mark fast, accurate and simple. The models and structures of all the designed alignment marks will make it easier for engineers to choose the property alignment mark faced with single patterning or SADP process.