Security Primitives Research Articles

A New Security Boundary of Component Differentially Challenged XOR Pufs Against Machine Learning Modeling Attacks

Physical Unclonable Functions (PUFs) are promising security primitives for resource-constrained network nodes. The XOR Arbiter PUF (XOR PUF or XPUF) is an intensively studied PUF invented to improve the security of the Arbiter PUF, probably the most lightweight delay-based PUF. Recently, highly powerful machine learning attack methods were discovered and were able to easily break large-sized XPUFs, which were highly secure against earlier machine learning attack methods. Component-differentially-challenged XPUFs (CDC-XPUFs) are XPUFs with different component PUFs receiving different challenges. Studies showed they were much more secure against machine learning attacks than the conventional XPUFs, whose component PUFs receive the same challenge. But these studies were all based on earlier machine learning attack methods, and hence it is not clear if CDC-XPUFs can remain secure under the recently discovered powerful attack methods. In this paper, the two current most powerful two machine learning methods for attacking XPUFs are adapted by fine-tuning the parameters of the two methods for CDCXPUFs. Attack experiments using both simulated PUF data and silicon data generated from PUFs implemented on field-programmable gate array (FPGA) were carried out, and the experimental results showed that some previously secure CDC-XPUFs of certain circuit parameter values are no longer secure under the adapted new attack methods, while many more CDC-XPUFs of other circuit parameter values remain secure. Thus, our experimental attack study has re-defined the boundary between the secure region and the insecure region of the PUF circuit parameter space, providing PUF manufacturers and IoT security application developers with valuable information in choosing PUFs with secure parameter values.

Genetic physical unclonable functions in human cells.

A physical unclonable function (PUF) is a physical entity that provides a measurable output that can be used as a unique and irreproducible identifier for the artifact wherein it is embedded. Popularized by the electronics industry, silicon PUFs leverage the inherent physical variations of semiconductor manufacturing to establish intrinsic security primitives for attesting integrated circuits. Owing to the stochastic nature of these variations, photolithographically manufactured silicon PUFs are impossible to reproduce (thus unclonable). Inspired by the success of silicon PUFs, we sought to create the first generation of genetic PUFs in human cells. We demonstrate that these PUFs are robust (i.e., they repeatedly produce the same output), unique (i.e., they do not coincide with any other identically produced PUF), and unclonable (i.e., they are virtually impossible to replicate). Furthermore, we demonstrate that CRISPR-engineered PUFs (CRISPR-PUFs) can serve as a foundational principle for establishing provenance attestation protocols.

A survey on silicon PUFs

Integrated Circuits (ICs) and electronic devices have become an integral part of daily human life (mobile, home, car, etc.). However, specific security measures should be taken to protect the communicated information to and from these devices. However, the existing conventional security primitives require large amounts of memory capacity, processing power, and energy resources that contradict the specific nature of devices. On the other hand, they store secret keys on the devices for future use, making them vulnerable to physical attacks. A new concept, known as Physically Unclonable Functions (PUFs), has been recently investigated to mitigate this problem. A PUF is a hardware-specific security primitive uses the randomness found in the disorder of physical media caused by the manufacturing variation process to provide cryptographic functionalities. Consequently, PUFs are inexpensive to fabricate, prohibitively challenging to duplicate, admit no compact mathematical representation, and are intrinsically tamper-resistant. This manuscript gives a complete survey of PUFs as a promising research field in security with a wide application, especially with connected devices. First, we motivate our contribution by comparing it with the existing surveys about PUFs. Then we provide the needed background to understand PUF architectures and applications by covering: the variability and randomness concepts, their classes, and properties. Then, we survey the existing initiatives related to silicon PUFs in terms of implementation and design used to extract unique secret information from the physical characteristics of an integrated circuit. In addition, we compare the surveyed works in terms of performance and security. Furthermore, we classify and compare the existing silicon PUF applications and use cases. Before concluding, we give the principal metrics used to evaluate the PUFs’ performance and present some related attacks. Finally, we talk about the current limitations of silicon PUF architectures and applications, and we look at and talk about research opportunities and major trends.

A reconfigurable PUF structure with dual working modes based on entropy separation model

Privacy Protection Mutual Authentication (PPMA) in the Internet of Things uses physical unclonable functions (PUFs) and true random number generators (TRNGs) as security primitives, providing a lightweight solution for key generation and protection. At present, the designs for achieving PUF and TRNG simultaneously on field programmable gate array (FPGA) lack theoretical support, and have poor randomness and stability. Therefore, this paper provides a separation model of PUF entropy (manufacturing delay) and TRNG entropy (jitter delay) based on ring oscillators (ROs). Based on this model, a reconfigurable PUF structure is proposed, which can be reconstructed to a TRNG by changing the working mode. The proposed structure not only improves the area utilization, but also realizes the low-power consumption. Experiments on Xilinx Spartan-6 FPGAs and Xilinx Virtex-6 FPGAs show that the proposed structure has wonderful performance. The PUF has excellent uniqueness (average resolution is 50.21%) and reliability (the average repeatability rate is 96.98%). TRNG's output sequences have high randomness and pass all National Institute of Standards and Technology (NIST) tests (average pass rate is 99%).

Agile-AES: Implementation of configurable AES primitive with agile design approach

In the data-centric era, interconnected devices must be able to communicate efficiently and securely with their hosts even over untrusted networks. This led to the adoption of several end-to-end security protocols that employ various efficient and elegant encryption algorithms, such as Advanced Encryption Standard (AES), often implemented with hardware modules since there is usually no good solution to install security software on the device itself. State-of-the-art AES hardware implementations typically focus on optimizing a single metric, e.g. throughput or area, and are tedious to adapt to a wider set of design constraints. Applying an agile approach to hardware development is increasingly important, and this is especially critical for hardware security primitives that need to be consumed in various systems. In this work, we develop Agile-AES, an open-source, flexible, parameterizable, hardware implementation of AES, combining many best-known practices. The agile and feature-rich implementation was based on the Chisel framework, through which flexibility is instrumented to support various key length, topology, mode of operation, local memory type, S-box fabric, side-channel attack defense techniques, and interfaces. Despite covering a larger design space, our proposed implementation has 50% fewer lines of code compared to existing Verilog versions — a crucial advantage in terms of maintainability and development productivity. To evaluate the QoR out of this implementation approach, we pick representative configurations and evaluate utilization, power and throughput on both entry level and server-grade FPGAs and compare against the Verilog and HLS counterpart implementations. It shows very comparable results to the Verilog implementation and better QoR compared to the HLS-based implementation.

A Subspace Pre-Learning Strategy to Break the Interpose PUF

Physical Unclonable Functions (PUFs) are promising security primitives for resource-constrained IoT devices. A critical aspect of PUF security research is to identify all potential security risks. This information about vulnerabilities is beneficial for both PUF developers and PUF-using application developers in terms of designing new PUFs to mitigate existing risks and avoid vulnerable PUFs. Recently, a PUF structure called Interpose PUF (IPUF) was proposed, which claims to be resistant to reliability attacks and machine learning modeling attacks. Related studies on this secure PUF design have demonstrated that some IPUFs can still be broken, but large IPUFs may remain secure against all known modeling attacks. In addition, all these studies either focus on plain challenge–response pair attacks or require prior knowledge of IPUF architecture implementation. However, depending on the claim of attack resistance to reliability attacks, we can employ a different attack approach to break IPUFs. In this paper, we describe a subspace pre-learning-based attack method that can rapidly and accurately break the IPUFs that were treated as secure in the earlier study, revealing a vulnerability in IPUFs if the open interface conforms to the way challenge–response data are accessed by the subspace pre-learning-based attack method.

Secret-free security: a survey and tutorial

“Classical keys,” i.e., secret keys stored permanently in digital form in nonvolatile memory, appear indispensable in modern computer security—but also constitute an obvious attack target in any hardware containing them. This contradiction has led to perpetual battle between key extractors and key protectors over the decades. It is long known that physical unclonable functions (PUFs) can at least partially overcome this issue, since they enable secure hardware without the above classical keys. Unfortunately, recent research revealed that many standard PUFs still contain other types of “secrets” deeper in their physical structure, whose disclosure to adversaries breaks security as well: Examples include the manufacturing variations in SRAM PUFs, the power-up states of SRAM PUFs, or the signal delays in Arbiter PUFs. Most of these secrets have already been extracted in viable attacks in the past, breaking PUF-security in practice. A second generation of physical security primitives now shows potential to resolve this remaining problem, however. In certain applications, so-called Complex PUFs, SIMPLs/PPUFs, and UNOs are able to realize not just hardware that is free of classical keys in the above sense, but completely “secret-free” instead. In the resulting hardware systems, adversaries could hypothetically be allowed to inspect every bit and every atom, and learn any information present in any form in the system, without being able to break security. Secret-free hardware would hence promise to be innately and permanently immune against any physical or malware-based key-extraction: There simply is no security–critical information to extract anymore. Our survey and tutorial paper takes the described situation as starting point, and categorizes, formalizes, and overviews the recently evolving area of secret-free security. We propose the attempt of making hardware completely secret-free as promising endeavor in future hardware designs, at least in those application scenarios where this is logically possible. In others, we suggest that secret-free techniques could be combined with standard PUFs and classical methods to construct hybrid systems with notably reduced attack surfaces.

A 10pJ/bit 256b AES-SoC Exploiting Memory Access Acceleration

Low-cost high-volume internet of things sensors require an end-to-end secure private-content exchange. Restricted energy and computing of system-on-a-chip for low-cost sensor applications drive lightweight hardware acceleration of security primitives. A trade-off between power and time needs to be achieved to develop such primitives. The main challenge is to handle memory transportation in the crypto-accelerator. Here we propose different approaches for AES-128/256 Sbox acceleration schemes. We designed a Sbox unit to be connected as a logic unit. The unit was tested as a RISC-V ISA instruction in the RISC-V processor to reduce software execution times. This unit was also included in an AES hardware core with direct memory access (DMA), which avoids using the main processor to access the data. We fabricated a RISC-V based 32-bit SoC in a standard 180nm CMOS technology that includes the Sbox calculation using pipeline and a pure-combinational approach. Measurement results indicate lower memory access and lower energy requirements than pure software approaches up to 100 times with a custom Sbox instruction. The AES core also provides a minimum energy consumption of 3.58 pJ/cycle. At its best, the combined SoC performs the encryption in active-mode with energy consumption of 9.7 pJ/bit. This solution offers up to three times energy savings compared to previously reported work.

Cryptographic pointers for fine-grained file access security

ABSTRACT We present a paradigm for fine-grained access security in a protection environment featuring files and records. Files are allocated at increasing addresses in a virtual space whose size is extremely large, so that virtual space reuse is never necessary. A record is a portion of a file. A subject certifies possession of an access privilege for a given object, file, or record, by presenting a cryptographic pointer (c-pointer) referencing that object. The c-pointer includes a key, and the composition of the access privilege expressed in terms of the two access rights, to read and to write. The c-pointer is valid if the key descends from a master key indicated in the c-pointer, by application of a universally known, symmetric algorithm. Records can be encrypted, and the key is specific to the given record. A set of security primitives forms the user interface of the security system. The resulting environment is evaluated from a number of viewpoints that include key proliferation, weakening and revocation, selective encryption, file directories, and robustness against security attacks aimed at c-pointer forging.

SPoTKD: A Protocol for Symmetric Key Distribution Over Public Channels Using Self-Powered Timekeeping Devices

In this paper, we propose a novel class of symmetric key distribution protocol that leverages basic security primitives offered by low-cost, hardware chipsets containing millions of synchronized self-powered timers. The keys are derived from the temporal dynamics of a physical, micro-scale time-keeping device which makes the keys immune to any potential side-channel attacks, malicious tampering, or snooping. Using the behavioral model of the self-powered timers, we first show that the derived key-strings can pass the randomness test as defined by the National Institute of Standards and Technology (NIST) suite. The key-strings are then used in two SPoTKD (Self-Powered Timer Key Distribution) protocols that exploit the timer’s dynamics as one-way functions: (a) protocol 1 facilitates secure communications between a user and a remote Server; and (b) protocol 2 facilitates secure communications between two users. In this paper, we investigate the security of these protocols under standard model and against different adversarial attacks. Using Monte-Carlo simulations, we also investigate the robustness of these protocols in the presence of real-world operating conditions and propose error-correcting SPoTKD protocols to mitigate these noise-related artifacts.

On the Unbearable Lightness of FIPS 140–2 Randomness Tests

Random number generation is critical to many applications. Gaming, gambling, and particularly cryptography all require random numbers that are uniform and unpredictable. For testing whether supposedly random sources feature particular characteristics commonly found in random sequences, batteries of statistical tests are used. These are fundamental tools in the evaluation of random number generators and form part of the pathway to certification of secure systems implementing them. Although there have been previous studies into this subject (Becker, 2013), RNG manufacturers and vendors continue to use statistical tests known to be of dubious reliability, in their RNG verification processes. Our research shows that FIPS-140-2 cannot identify adversarial biases effectively, even very primitive ones. Concretely, this work illustrates the inability of the FIPS 140 family of tests to detect bias in three obviously flawed PRNGs. Deprecated by official standards, these tests are nevertheless still widely used, for example in hardware-level self-test schemes incorporated into the design of many True RNGs (TRNGs). They are also popular with engineers and cryptographers for quickly assessing the randomness characteristics of security primitives and protocols, and even with manufacturers aiming to market the randomness features of their products to potential customers. In the following, we present three <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">biased-by-design</i> RNGs to show in explicit detail how simple, glaringly obvious biases are not detected by any of the FIPS 140–2 tests. One of these RNGs is backdoored, leaking key material, while others suffer from significantly reduced unpredictability in their output sequences. To make our point even more straightforward, we show how files containing images can also fool the FIPS 140 family of tests. We end with a discussion on the security issues affecting an interesting and active project to create a randomness beacon. Their authors only tested the quality of their randomness with the FIPS 140 family of tests, and we will show how this has led them to produce predictable output that, albeit passing FIPS fails other randomness tests quite catastrophically.

Secure Electronics Enabled by Atomically Thin and Photosensitive Two-Dimensional Memtransistors.

The rapid proliferation of security compromised hardware in today's integrated circuit (IC) supply chain poses a global threat to the reliability of communication, computing, and control systems. While there have been significant advancements in detection and avoidance of security breaches, current top-down approaches are mostly inadequate, inefficient, often inconclusive, and resource extensive in time, energy, and cost, offering tremendous scope for innovation in this field. Here, we introduce an energy and area efficient non-von Neumann hardware platform providing comprehensive and bottom-up security solutions by exploiting inherent device-to-device variation, electrical programmability, and persistent photoconductivity demonstrated by atomically thin two-dimensional memtransistors. We realize diverse security primitives including physically unclonable function, anticounterfeit measures, intellectual property (IP) watermarking, and IC camouflaging to prevent false authentication, detect recycled and remarked ICs, protect IP theft, and stop reverse engineering of ICs.

FVCARE: Formal Verification of Security Primitives in Resilient Embedded SoCs

FVCARE: Formal Verification of Security Primitives in Resilient Embedded SoCs

Neural Network Physically Unclonable Function: A Trainable Physically Unclonable Function System with Unassailability against Deep Learning Attacks Using Memristor Array

Security Primitives In article number 2100111, Shinhyun Choi and co-workers propose a trainable security primitive integrated with deep neural network and memristor arrays. The entire system can achieve optimal performance for security metrics by training. In the cover image, the trained encryption system only allows access to confidential information through an authenticated code (denoted by a blue key) and secures the information from adversaries (denoted by red keys).

Design and Implementation of Novel Design Methodology for Securing the Internet of Things Applications

Typically, in the Internet of Things (IoT) yields objects are controlled and monitored remotely over a network. A standard IoT system includes various sensors that combine with microprocessors and other custom peripherals to perform their operations. Data collection and processing, computation, and finally communication these operations are involved to carry out IoT applications. Designer and user both demand these operations should be performed without any kind of unauthorized interference. As per the current trend, the way we have relied on technology, the way data exchange has started, it is not possible to rely on existing data security systems. It has become imperative to add a concrete solution to the existing infrastructure of security. Hardware security is attracted attention of researchers because of its importance in IoT applications, IP securities, and controlling counterfeit electronic devices. Physically Unclonable Functions (PUF) is an innovative approach that provides security primitives and also will resist Integrated Circuit (IC) cloning and counterfeiting. PUF works on the principle of process variations present inside the hardware. PUFs carry capricious and event-specific values and can be used to provide hardware security. Nowadays IoT design has been implemented on the SoC platform. Here we have designed PUF on the SoC platform so that it will be helpful to IoT designs. The presented work will help in understanding the ROPUF design with respect to simulation, synthesis, placement and routing and hardware validation.

Neural Network Physically Unclonable Function: A Trainable Physically Unclonable Function System with Unassailability against Deep Learning Attacks Using Memristor Array

The dissemination of edge devices drives new requirements for security primitives for privacy protection and chip authentication. Memristors are promising entropy sources for realizing hardware‐based security primitives due to their intrinsic randomness and stochastic properties. With the adoption of memristors among several technologies that meet essential requirements, the neural network physically unclonable function (NNPUF) is proposed, a novel PUF design that takes advantage of deep learning algorithms. The proposed design integrated with the memristor array can be constructed easily because the system does not depend on write operation accuracy. To contemplate a nondifferentiable module during training, an original concept of loss called PUF loss is devised. Iterations of weight update with the loss function bring about optimal NNPUF performance. It is shown that the design achieves a near‐ideal 50% average value for security metrics, including uniformity, diffuseness, and uniqueness. This means that the NNPUF satisfies practical quality standards for security primitives by training with PUF loss. It is also demonstrated that the NNPUF response has an unassailable resistance against deep learning‐based modeling attacks, which is verified by the near‐50% prediction model accuracy.

ARMOR: An Anti-Counterfeit Security Mechanism for Low Cost Radio Frequency Identification Systems

Counterfeited products are costing the global economy hundreds of billions of dollars annually. Radio frequency identification(RFID) technology provides a promising solution for this problem, wherein each product is fitted with a secure tag, which is difficult to forge. However, RFID technology is faced with numerous security threats, for example, if the communication link between the reader and the tag is compromised, then it will be possible for a malicious adversary to obtain the private data stored on the device. Tag cloning attacks have also been demonstrated to be feasible, which severely undermines the capabilities of the RFID technology to protect against counterfeiting. One solution to this problem is the use of authentication protocol; however, existing schemes do not support mutual authentication and are still vulnerable to tag cloning attacks. In this article, a new security mechanism is proposed, which consists of a lightweight three-flights mutual authentication protocol and an anti-counterfeit tag design. The proposed solution is based on combining the Rabin public-key encryption scheme with physically unclonable functions (PUF) technology. The security of the proposed protocol is systematically analysed and compared with existing schemes. The implementation cost of the proposed security primitives, assuming the 1024-bit public key, is 10139 GEs, which is suitable for low-cost RFID tags. Our results show that the proposed design is up-to 50 percent more area-efficient compared to systems based on Elliptic Curve Cryptography (ECC).

Survey on the benefits of using memristors for PUFs

This paper reviews memristive PUFs (Physical Unclonable Functions) reported in the literature. The paper explains the motivation for using memristor technology for implementing PUFs. It focuses on PUFs’ applications, sizes, analysis, and physical variations. In addition, the paper presents the number of samples generated using Monte Carlo simulation for evaluating the PUF circuits. This paper also describes the protocols, functionality, and methodologies proposed in the memristive PUF literature. Although memristive PUFs are not commercialized yet, there is a high expectation of exploiting the memristors as fundamental elements in the next generation of hardware security primitives (e.g. PUF) due to their unique characteristics such as forming process, temporal drift, nonlinearity, bidirectionality, nonvolatility and model complexity. There have been some survey papers on memristor PUFs in the past, however, the field has continued to develop so a comprehensive survey including recent publications seemed in order at this time. Lately, memristor technology improvement has accelerated, therefore creating a need for an updated survey of the applications of memristors for PUFs.

A robust architecture of physical unclonable function based on Memristor crossbar array

During the past two decades, Physical Unclonable Functions (PUF) remained under discussion as strong hardware security primitives. As compared to conventional technology, memristor-based PUFs got tremendous attraction due to their simple and easy architecture, high endurance, low energy consumption, small size, and low cost. The inherent high variability of memristive devices makes it an ideal candidate for the generation of unique fingerprints for individual devices. By exploiting this variation, we propose a novel architecture dual memristive crossbar (DuMXbar) that integrates two memristive crossbar PUFs implemented with two different memristor devices. Each PUF generates highly uncorrelated response pairs. The simulation results of DuMXbar PUF prove that it is comparatively more robust against machine learning (ML) based classification algorithms like logistic regression and support vector machine. We have also proposed a secure authentication protocol for DuMXbar PUF to restrict the prediction accuracy of ML algorithms close down to 50% (ideal).

Application of Resistive Random Access Memory in Hardware Security: A Review

AbstractNowadays, advancements in the design of trusted system environments are relying on security provided by hardware‐based primitives, while replacing resource‐hungry software security measures. Emerging nonvolatile memory devices are promising candidates to provide the required hardware security functionalities at very low area‐energy‐runtime budget. Resistive random access memory (RRAM) offers high‐density integration with outstanding performance among the state‐of‐the‐art nonvolatile memory devices. The RRAM device technology is currently getting significant attention from both academia and industry for constructing beyond Von Neumann architectures. This technology's strength is its scalable two‐terminal structure, the availability of wide range of functional materials, and multi‐bit storage capability. The fluctuations in switching resistances, random telegraph noise, and sneak path current are detrimental characteristics of RRAM integrations for storage and in‐memory computing applications, and more research focuses on alleviating these effects. Interestingly, these characteristics make them suitable for designing security hardware. In recent times, there has been significant progress in the design and analysis of RRAM‐based security primitives such as, Physical Unclonable Function, true random number generator, and hash function. This review discusses the detailed developments in RRAM security and presents the demanded security requirement and available opportunities to be explored.