Electrically active defects that either trap carriers or act as centers of fixed charge are critically important in MOS devices. Their effects are particularly pronounced for arsenide-based semiconductors intended for NMOS devices because of 1) the relative ease of forming surface defects on these crystals, 2) the lack of an insulating native oxide (such a SiO2) to inhibit tunneling of electrons from the substrate into near-interface defects in deposited gate dielectrics, and 3) the low density of states in the conduction band of the semiconductor that enhances the effect of charge traps on the measured capacitance compared to materials such as Si or Ge. Alloying GaAs with InAs reduces the band gap of the former by lowering the energy of the conduction band edge, reducing the overall density of defect states in the band gap and thus the density of interface traps. Further reduction in both bulk dielectric defect densities (e.g. border traps and fixed charge) and interface trap densities can be achieved by appropriate pre-dielectric and post-dielectric processes. This presentation will review recent results on pre-atomic layer deposition defect passivation, including trimethyl aluminum pre-dosing of initially clean and oxide-free InGaAs (100) surfaces, plasma treatments of initially air-exposed surfaces, and post-dielectric defect passivation using hydrogen. Reliable interface trap density measurements that combine capacitance-voltage and conductance-voltage analysis indicate decreasing trend in interface trap density across the band gap from the valence band to the conduction band edge, and can distinguish the influence of these defects from the response of border traps in the oxide. Results obtained from ALD-Al2O3 MOS capacitors fabricated on As2-decapped InGaAs (100) substrates are compared with reported density functional theory predictions and scanning probe measurements of InGaAs surface defect passivation, showing the potential of pre-ALD dosing of the (100) substrate with trimethyl aluminum (TMA) to reduce interface trap densities across the band gap, with Dit < 1012 cm2eV-1 in the upper half of the InGaAs band gap. Apart from oxide/InGaAs interface traps, border traps in the oxide may also reduce the charge in the channel and thus degrade the on-state performance of InGaAs MOSFET devices. Results are reported on of the effects of various approaches to reduce the density of border traps (N bt), such as variation of the ALD temperature, and of post-gate metal forming gas (5% H2/95% N2) anneal (FGA) conditions. Quantitative border trap modeling of MOS capacitor data obtained over a range of frequencies and measurement temperatures indicate that Al2O3 MOS capacitors fabricated using a standard TMA/H2O ALD chemistry at 120°C have a 2X-3X lower border trap density, without increasing D it, compared to samples prepared at a more standard 270°C Al2O3 ALD temperature. The reduction of N bt with decreasing ALD process temperature is consistent with time-of-flight secondary ion mass spectrometry depth profiles that show more effective hydrogen incorporation in the low-temperature ALD-grown Al2O3 films during post-gate FGA. The nature of border trap response in low-temperature ALD-HfO2 films will also be reported, and compared to ALD-Al2O3. Pre-ALD InGaAs surface preparation conditions are found to strongly influence Dit for low-T ALD-HfO2 MOS capacitors, but has no effect Nbt .
Read full abstract
Mar 28, 2016
S Gruber + 4
Open Access