Second-order Loop Research Articles

Research on Friction Compensation Method of Electromechanical Actuator Based on Improved Active Disturbance Rejection Control

The friction factor of harmonic reducers affects the transmission accuracy in electromechanical actuators (EMAs). In this study, we proposed a friction feedforward compensation method based on improved active disturbance rejection control (IADRC). A mathematical model of EMA was developed. The relationship between friction torque and torque current was derived. Furthermore, the compound ADRC control method of second-order speed loop and position loop was studied, and an IADRC control method was proposed. A real EMA was developed, and the working principles of the EMA driving circuit and current sampling were analyzed. The three methods—PI, ADRC, and IADRC—were verified by conducting speed step experiments and sinusoidal tracking experiments. The integral values of time multiplied by the absolute error of the three control modes under the step speed mode were approximately 47.7, 32.1, and 15.5, respectively. Disregarding the inertia of the reducer and assuming that the torque during no-load operation equals the friction torque during constant motion, the findings indicate that, under a load purely driven by inertia, the IADRC control method enhances tracking accuracy.

Meta-material inspired penta-band decagon fractal antenna for wireless applications

In this article, a meta-material inspired penta-band fractal antenna is proposed for wireless applications. It is constructed by integrating the Complementary Split Ring Resonator (CSRR) and decagon fractal structure. The decagon is the regular polygon with 10 sides. Three layers are constructed in the proposed design to obtain the multiple operating frequencies with better performance. Top layer has the decagon structure with ten slots and second-order Koch loop radiating element. The rectangular patch layer and CSRR layer are the bottom layers. Dielectric material FR4 is selected to design the suggested antenna. The measurement results reveal that the projected antenna has five resonant frequencies at 2.63 GHz, 3.98 GHz, 4.78 GHz, 5.52 GHz and 5.91 GHz with a bandwidth of 230 MHz, 300 MHz, 80 MHz, 200 MHz, and 290 MHz. Gain is observed about 3.29 dB, 4.44 dB, 5.71 dB, 4.22 dB and 3.99 dB at the corresponding resonant frequencies.

Performance analysis of a normal GNSS receiver model under different types of jamming signals

Global Navigation Satellite System (GNSS) performance can be significantly degraded by jamming signals, especially for off-the-shelf civil receivers being characterized by poor anti-jamming ability. Although numerous anti-jamming algorithms have been developed to improve GNSS performances, little is known about impacts of jamming signals on normal receivers' stability. To investigate the performance of normal receivers under jamming signals with different types and jamming-to-signal ratios (J/S), we analyzed the effective carrier-to-noise ratio (C/N0) of normal GNSS receivers with second-order tracking loops, and then investigated the minimum J/S causing loss-of-lock in normal receivers. This minimum J/S provides a J/S threshold that anti-jamming algorithms should be activated. Moreover, it is a baseline to guide the selection of effective anti-jamming algorithms. The results show that, when tracking threshold is 28 dB·Hz of the effective C/N0, the J/S thresholds for single-tone, multi-tone, bandlimited noise and white noise are 38 dB, 40 dB, 35 dB and 41 dB, respectively.

A low noise 2.2 GHz PLL ASIC for the CSR external-target experiment

This paper presents the design and test results of a low noise Phase Locked Loop (PLL) Application Specific Integrated Circuit (ASIC), which is designed for the data transmission system in a pixel chip for a beam monitor of the Cooling Storage Ring (CSR) external target experiment at HIRFL in China. The proposed PLL consists of a differential ring oscillator, a digital divider, a three-state phase frequency detector, a current charge pump, a second-order loop filter and current mode level buffers. A prototype PLL ASIC has been fabricated in a standard 130 nm CMOS process. The test results show that the frequency of the output clock is about 2.2 GHz with a phase noise of −90 dBc/Hz at a frequency offset of 1 MHz and a root mean square jitter of 1.15 ps. The core circuit of the PLL consumes about 30 mW under the power supply of 1.2 V.

On the limit behavior of second-order analog phase-locked loops

The study of limit behavior of a dynamical system is necessary for nonlinear analysis and computation of the exact boundary of global stability in the parameters’ space. For phase-locked loops (PLLs), a problem of its global stability is equal to a problem of a pull-in range calculation, which is one of the key stability characteristics of a PLL. In this paper, we consider a model of a second-order analog PLL and show that it can exhibit a wide range of limit behavior, including cycles and polycycles of the first and second kind.

The Gardner Problem and Cycle Slipping Bifurcation for Type-2 Phase-Locked Loops

In the present work, a second-order type-2 phase-locked loop (PLL) with a piecewise-linear phase detector characteristic is analyzed. An exact solution to the Gardner problem on the lock-in range is obtained for the considered model. The solution is based on a study of cycle slipping bifurcation, which improves the well-known engineering estimates.

Sensorless Control Strategy for BLDC Motors Based on a Type-3 Phase Locked Loop

This paper presents the design procedure of a high-performance sensorless control strategy for the widely used brushless DC (BLDC) motors. Generally, conventional sensorless techniques are based on detecting the zero-crossing instants (ZCP) of the back electromotives forces (back-EMFs) of the three phases. These methods, although widely adopted and marketed on an industrial level, involve many limitations such as filtering delays, difficulty to operate at low speeds and immunity against Electromagnetic Interferences (EMI). In this paper, the main objective is to develop a sensorless control technique integrally independent from the zero-crossing points of the back-EMFs. In the proposed method, a zero-delay adaptive filter was used to extract the fundamental and the quadrature components of the line-to-line voltage of the motor. Then, the Synchronous Reference Frame Phase Locked Loop (SRF-PLL) is used to estimate the electrical angle of phase-to-phase back-EMF along with the rotor speed. The conventional SRF-PLL was implemented using a second-order loop filter (type-3 PLL) in order to improve synchronization performances and for better rejection of voltage spikes induced in motor phases during commutations. The benefits of the control technique are brought to light through simulation results. An experimental prototype was designed to confirm the validity of the proposed method.

Multiplexed sensing interrogation technique based on a flexibly switchable multi-passband RF filter by using a Solc-Sagnac loop.

In this paper, we have proposed and experimentally demonstrated a multiplexed sensing interrogation technique based on a flexibly switchable multi-passband RF filter with a polarization maintaining fiber (PMF) Solc-Sagnac loop. A high-order Solc-Sagnac loop can be used as a spectrum slicer as well as sensing heads, and a multi-passband microwave photonic filter (MPF) can be achieved together with a dispersive medium. Environmental parameter variations will cause a frequency shift of the corresponding passband of the MPF, so by employing only one Sagnac loop, it is possible to monitor several environmental parameters simultaneously. In this article, we have demonstrated and analyzed the performance of the flexibly switchable multi-passband MPF by using a second-order Solc-Sagnac loop. To demonstrate the temperature sensing capabilities of our interrogation system, we have applied temperature changes individually to Sensor Head 1 (L P M F 1 ≈0.97m) only, Sensor Head 2 (L P M F 2 ≈2.97m) only, and both Sensor Head 1 and 2 in the experiment. By monitoring frequency shift of the MPF's passbands, the sensitivities for Sensor Head 1 and Sensor Head 2 have been estimated to be -0.275 ± 0.011 MHz/℃ and -0.811 ± 0.013 MHz/℃ respectively, which show a good sensing linearity and stability. By utilizing the longer length of the sensing PMF, higher sensitivity can be achieved. By using Solc-Sagnac loop with higher order, more sensors can be multiplexed.

A Blind Demodulation Algorithm for Underwater Acoustic MPSK Signal

Multiple phase-shift keying (MPSK) is a common carrier modulation in underwater acoustic (UWA) communication. This paper proposes a robust blind demodulation algorithm to improve the performance and practicability of blind demodulation of MPSK signals under impulsive noise and UWA sparse multipath channels. The proposed algorithm adopts a $T$ /2-spaced blind equalizer based on quasi-affine projection, so it has strong adaptability to sparse UWA multipath channels. First, the received signal is preprocessed to suppress the impulsive interference, and the parameters are estimated. Then, timing synchronization is performed point by point based on sliding discrete Fourier transform (SDFT) to avoid equalizer performance degradation or even lock-loss caused by large clock frequency deviation and long-time error accumulation. Based on this, the over-sampling signal with two fixed sampling points per symbol is obtained. Meanwhile, following the idea of memory improved proportionate affine projection algorithm and normalized factor, the cost function of the blind equalizer is constructed by using the $l_{0}$ norm penalty on the tap coefficients. In this way, the updating formula of the tap coefficients is derived, and the blind equalization is then conducted on the signal after timing synchronization to eliminate or weaken the channel influence. Finally, the residual frequency offset and phase offset of the carrier are removed through the M-power transform and the second-order decision feedback digital phase-locked loop. Simulation experiments and practical signal demodulation results indicate that the proposed algorithm achieves higher BER performance and modulation parameter robustness for impulsive noise and UWA multipath channel.

A 6.5-μW 10-kHz BW 80.4-dB SNDR Gm-C-Based CT ∆∑ Modulator With a Feedback-Assisted Gm Linearization for Artifact-Tolerant Neural Recording

This article presents a Gm-C-based continuous-time delta-sigma modulator (CTDSM) for artifact-tolerant neural recording interfaces. We propose the feedback-assisted Gm linearization technique, which is applied to the first Gm-C integrator by using a resistive feedback digital-to-analog converter (DAC) in parallel to the degeneration resistor of the input Gm. This enables the input Gm to process the quantization noise, thereby improving the input range and linearity of the Gm-C-based CTDSM, significantly. An energy-efficient second-order loop filter is realized by using a voltage-controlled oscillator (VCO) as the second integrator and a phase quantizer. A proportional-integral (PI) transfer function is employed at the first integrator, which minimizes the output swing while maintaining loop stability. Fabricated in a 110-nm CMOS process, the prototype CTDSM achieves a high input impedance, 300-mVpp linear input range, 80.4-dB signal-to-noise and distortion ratio (SNDR), 81-dB dynamic range (DR), and 76-dB common-mode rejection ratio (CMRR) and consumes only 6.5 μW with a signal bandwidth of 10 kHz. This corresponds to a figure of merit (FoM) of 172.3 dB, which is the state of the art among the neural recording ADCs. This work is also validated through the in vivo experiment.

Effect of Topological Defects on the Elasticity of Near-Ideal Polymer Networks

AbstractIn recent years, new types of polymer gels have emerged, which have a well-controlled network structure and few topological defects. These so-called near-ideal polymer networks constitute a good model system to revisit the long-standing problem of structure–property relationships in polymer networks, as well as a promising platform for the development of polymer gels with outstanding mechanical properties. In this study, we investigate the relative contributions of network defects (dangling chains and second-order loops) on the stress–stretch response of near-ideal polymer networks using a computational discrete network model. We identify the average chain prestretch as a key parameter to capture the effect of network topology on the elastic modulus and maximum extensibility. Proper account of the chain prestretch further leads to scaling relations for the elastic properties in terms of topology parameters that differ from classical estimates of rubber elasticity theory. Stress–stretch curves calculated using the discrete network model are also compared to semi-analytical estimates.

Second‐order lead compensator‐based quadrature PLL for sensorless interior permanent magnet synchronous motor control

To eliminate harmonic components in estimated speed and position information generated by inverter non-linearities for the interior permanent-magnet synchronous motor (IPMSM) sensorless control, a second-order lead compensator-based quadrature phase-locked loop (SOLC-Q-PLL) is proposed for the sliding mode observer. An adaptive super-twisting sliding mode observer is taken to estimate back electromotive forces (EMFs) for IPMSM. Harmonic components in estimated position information generated by inverter non-linearities are analysed. Being dependent on the corresponding analysis, the SOLC-Q-PLL is proposed to eliminate sixth position estimation errors only by introducing a second-order lead compensator without causing phase delay for the phase-locked loop system. The introduction of the second-order lead compensator does not influence the bandwidth of the phase-locked loop system so that a fast transient response can be achieved, and this algorithm is easy to implement digitally due to its simple structure. Eventually, a series of experiments are conducted to validate the capability of the proposed algorithm.

Swing equation in power systems: Approximate analytical solution and bifurcation curve estimate.

The swing equation plays a central role in the model and analysis of power system dynamics, including small-signal stability and transient stability. As it has the same form as that in a variety of different disciplines, such as the forced pendulum in mechanics, the classical mechanistic description of superconducting Josephson junctions in physics, and the classical second-order phase-locking loop in electronics, it has aroused general interest in science and engineering. In this paper, its approximate solution of the limit cycle is obtained by means of the incremental harmonic balance (IHB) method. It is found that the trouble of a more distorted limit cycle when the parameters are closer to the homoclinic bifurcation curve can be easily solved by incorporating higher order harmonics in the IHB method. In this way, we can predict the homoclinic bifurcation curve perfectly. In addition, the method is extended to study a generalized swing equation including excitation voltage dynamics.

A Novel Order Reduced Synchronous Power Control for Grid-Forming Inverters

Nowadays, the grid-forming inverter, also referred as the voltage-controlled inverter, has gained greater attention due to its advantages in providing power support to the grid. The power control is central to grid-forming inverters in realizing grid-support functionalities, such as the droop control or virtual inertia emulation. However, in these controls, the dynamic response of the instantaneous power usually suffers from overshoots and oscillations. To improve the dynamic response of the injected instantaneous power, this letter introduces a novel synchronous active power control for the voltage-controlled grid-connected inverter. The droop coefficient can be released from adjusting the damping factor of the system. A novel design method is proposed to reduce the second-order power loop to a first-order model. Consequently, the droop and reference-following controls operate like a first-order system with an excellent dynamic response. Moreover, the virtual inertia can be designed freely without affecting the performance of the power control. The correctness of the control is verified experimentally.

Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter

This paper provides an in-depth analysis of the third-order bang-bang clock and data recovery (BBCDR) circuit, which accurately predicts its operating characteristics, namely, the jitter transfer function (JTF), the jitter tolerance (JTOL), and the jitter generation (JGEN). By formulating the time-domain waveforms, we introduce a characterizing method and also derive the closed-form equations and their simplified versions under specific conditions, which are related with the second-order loop filter (LF). Our framework is consistent with the conclusions of the prior works. Also, we discuss through the time-domain behavior, the sinking area of the JTOL and other specific phenomenon appearing in the third-order BBCDR loop. We verify all above prediction by system-level simulations with the MATLAB/simulink model.

Real-Time Estimation for Roll Angle of Spinning Projectile Based on Phase-Locked Loop on Signals from Single-Axis Magnetometer.

As roll angle measurement is essential for two-dimensional course correction fuze (2-D CCF) technology, a real-time estimation of roll angle of spinning projectile by single-axis magnetometer is studied. Based on the measurement model, a second-order frequency-locked loop (FLL)-assisted third-order phase-locked loop (PLL) is designed to obtain rolling information from magnetic signals, which is less dependent on the amplitude and able to reduce effect from geomagnetic blind area. Method of parameters optimization of tracking loop is discussed in the circumstance of different speed and it is verified by six degrees of freedom (six degrees of freedom (DoF)) trajectory. Also, the measurement error is analyzed to improve the accuracy of designed system. At last, experiments on rotary table are carried out to validate the proposed method indicating the designed system is able to track both phase and speed accurately and stably. The standard deviation (SD) of phase error is no more than 3°.

Timing Jitter Distribution and Power Spectral Density of a Second-Order Bang–Bang Digital PLL With Transport Delay Using Fokker–Planck Equations

In this paper, a second-order bang-bang digital phase-locked loop (BBPLL) with dominant random walk phase noise and transport delay is analyzed using Fokker-Plank equations. Explicit closed-form expressions are derived for the timing error probability distribution function, jitter variance, and power spectral density (psd). For the type-II BBPLL considered in this paper, the timing error distribution is shown to be Laplacian and not Gaussian distributed as previously assumed, while the derived psd is Lorentzian, which is consistent with earlier works. The analytical solutions are valid as long as the continuous-time approximation of the BBPLL dynamics is accurate as is the case for typical operating loop bandwidths. The accuracy of the derived expressions is validated via simulation.

A Low Switching Noise and High-Efficiency Buck Converter Using a Continuous-Time Reconfigurable Delta-Sigma Modulator

This paper presents a delta-sigma modulation control scheme for buck converters that features a reconfigurable loop filter with a scalable sampling frequency for effective switching noise reduction and high conversion efficiency. Depending on the load current, the proposed controller changes the sampling frequency along with the delta-sigma modulator (DSM) structure to transform between third- and second-order loop filters. Thus, it maintains a robust noise shaping capability and reduces the power consumption over a wide load range. The loop filters are implemented with a single op-amp resonator to reduce multiple integrators into a single element and enhance controllability of the resonance. More power-efficient operation is obtained by a switching node assisted deadtime controller (SADTC) that regulates the body-diode conduction. The proposed DSM-based buck converter was fabricated on a 180 nm CMOS. A spurious-free output spectrum with a noise floor below −81 dBm was achieved across all sampling frequencies. It operated at a wide range sampling frequencies of 3.75–15 MHz and regulated the output in the range of 1.0–2.4 V with input voltages of 2.5–5.5 V. The output voltage ripples were maintained under 19 mV. The converter showed a conversion efficiency of better than 80% over a load range of 1–1000 mA with a peak efficiency of 95.4% at 125 mA.

A Robust Design of Active Damping With a Current Estimator for Single-Phase Grid-Tied Inverters

This paper presents an improved control scheme for the operation of grid-tied inverters in order to attain the IEEE 1547.2-2008 harmonic limit standard even with a wide range of grid parameters. This control structure includes an active damping with a new current estimator and a proportional-resonant controller with harmonic compensation. In order to guarantees the inverter operation with a wide range of grid parameters, the damping and the controller gains are designed considering robustness characteristics. Moreover, it proposes a new estimator for the current filter capacitor for operation with a wide range filter resonance frequency. The grid synchronization mechanism uses the modified second-order general integrator frequency-locked loop technique. Experimental results are carried out and presented to validate the control structure design and the proposed current estimation.

Performance Enhancement of PV-Fed Unified Power Quality Conditioner for Power Quality Improvement Using JAYA Optimized Control Philosophy

In this paper, the operation and control of photovoltaic-fed unified power quality conditioner in grid-connected mode including the power quality enhancement feature has been systematically examined. The current harmonics, voltage sags, voltage swells, voltage unbalance, dc-link voltage regulation are the primary factors limiting the performance of the AC system. Therefore, these power quality issues are needed to be eliminated by high-performance power conditioners controlled through highly effective control strategies. In this paper, an optimization algorithm is used to amplify the controller performance by achieving the best numerical parameters for proportional plus integral controller of PV-UPQC. Detail analysis involving elimination of current harmonics, voltage sags and voltage swells are investigated to analyze the effect of novel optimization algorithm on controller of photovoltaic-fed unified power quality conditioner system. In addition, this paper proposes double second-order integral quadrature signal generator-based phase-locked loop mechanism for proper grid synchronization. Finally, experimental verification of the performance of the proposed scheme by hardware prototype development has been included.