Search Motion Estimation Research Articles

FastInter360: A Fast Inter Mode Decision for HEVC 360 Video Coding

This paper presents FastInter360, a fast inter mode decision algorithm for accelerating the encoding of ERP 360 videos. The development of FastInter360 involves an in-depth and comprehensive set of evaluations performed to understand the differences in the encoder’s behavior when encoding 360 and conventional videos. These evaluations showed that due to the texture distortions resulting from projection, the encoder presents a specific behavior when encoding 360 videos, making it more likely to use a recurrent set of encoding modes when processing 360 videos. Besides, the coding efficiency is less sensible to approximations in some encoding steps depending on the frame region. FastInter360 is then proposed to reduce the encoding complexity by exploiting these differences. FastInter360 comprises three algorithms that accelerate the encoding by performing early decision by SKIP mode, reducing integer motion estimation search range, and adjusting fractional motion estimation precision. Furthermore, each of these algorithms behaves according to distortion intensity, performing greater complexity reduction in more distorted regions. When employed altogether, these algorithms compose FastInter360, which is able to achieve an average complexity reduction of 22.84% with a coding efficiency loss of 0.652% BD-BR, on average, making FastInter360 competitive with literature works.

Regressive rate-distortion trade-off with weighted entropy coding for HEVC encoding

High-Efficiency Video Coding (HEVC) is the standard employed for the subsequent compressing of the video without degrading the quality of the image. HEVC renders effective performance compared to the existing compression standards as the encoding time is minimal. With the concern for quality and video compression, this paper proposes a modified version for HEVC encoding using the Ordered Tree-based Hex-Octagon based block Search and Rate-Distortion trade-off (OrTHO-Search-based RD) for motion estimation and weighted Context-Adaptive Binary Arithmetic Coding (CABAC). The proposed OrTHO-Search-based RD-dependent HEVC renders a good-quality video after compression with half the compression standard when compared with the other existing compression standards. In the motion estimation block, the OrTHO-Search is employed with a new RD trade-off in such a way that the Conditional Autoregressive Value at Risk concept modifies the existing RD trade-off measure. The bit rates of the proposed method are reduced with effective coding. The experimentation and analysis of the methods are performed using four videos from CIPR SIF Sequences and one video from Xiph.org Video Test Media datasets and the analysis based on Peak Signal-to-Noise Ratio (PSNR), Structural Similarity Index (SSIM), reveals that the proposed method acquired the maximal PSNR of 45.1132 dB, maximal SSIM of 0. 9918, and minimal computational time of 0.2135 min.

Complexity reduction of test zonal search for fast motion estimation in uni-prediction of High Efficiency Video Coding

The complexity of motion estimation in the High Efficiency Video Coding (HEVC) standard is very high as it uses a number of prediction block sizes. The test zonal search (TZS) mechanism is used as motion estimation algorithm in the fast search mode of HM encoder, the reference software for HEVC. In this paper, we present schemes for reducing the complexity of the TZS algorithm for uni-prediction in HEVC. The proposed mechanisms help in reducing complexity of grid, raster and refinement search stages of TZS. The performance of the proposed mechanisms is tested independently and also combined in the fast search mode of HM-16.18. The motion estimation time and the number of search points in the combined algorithm are reduced by 68.14% and 77.10% with a BD-rate of 0.30% and a BD-PSNR of $$-0.007$$ dB in comparison with the original fast search mode in the low-delay P main profile. The proposed complexity reduction schemes are compared with those adopted in other recently proposed fast motion estimation algorithms and the performance of the proposed scheme is found to be superior in terms of the reduction in motion estimation time.

Multi‐objective genetic algorithm on hexagonal search for fast motion estimation

Motion estimation (ME) is a process of correlating the frames by pointing the blocks in the candidate frame similar to those in the previous frame. Hexagonal Search (HS) reduces 10–15% search points over Diamond Search (DS) with negligible Peak Signal to Noise Ratio (PSNR) loss. Adapting an optimization will achieve a massive improvement on the search process. The proposed HS-GA method combines the HS with genetic algorithm (GA) to optimize ME. The HS-GA method reduces 72% on average search points pre block (ASPB) with PSNR loss of 2.5 dB and single generation. If the GA is executed with 10 generations the PSNR loss is reduced to 0.48 dB, but ASPB drastically increase to ∼316%. The proposed work aims at multi objective on selection of better chromosomes and on control of generations to avoid the unnecessary generations to improve the GA. This process is named HSIGA(HS with Intelligent GA). The proposed HSIGA adapts five intelligent techniques like Histogram to decide new generations, Region based chromosome selection, Mutation on inner search gene, second rank valley point stopping criteria and interlaced HS to improve search process with negligible PSNR loss with in affordable search.

GPU-Based Hierarchical Motion Estimation for High Efficiency Video Coding

Motion estimation (ME) plays a crucial role in removing the temporal redundancy for video compression. However, during the encoding process a substantial computational burden is imposed by ME due to the exhaustive evaluations of possible candidates within the searching window. In view of the increasing computing capacity of GPU, we propose a GPU-based low delay parallel ME scheme for high efficiency video coding (HEVC). In particular, considering the quadtree coding structure of HEVC, we achieve the parallelization in a hierarchical way by optimizing the ME process in a coding tree unit (CTU), prediction unit (PU), and motion vector (MV) layers. Specifically, in the CTU layer, a novel motion vector predictor determination scheme is proposed to alleviate the side effects of inaccurate MV prediction due to the removal of the CTU-level dependency. In the PU layer, a novel indexing table is particularly designed to realize an efficient cost derivation strategy. As such, the cost of each PU can be computed in a convenient and efficient manner. In an MV layer, we propose a compact descriptor to represent MV and its corresponding cost as a whole, such that the redundant branches can be further avoided in the searching process. With such an optimization strategy, the proposed scheme can completely save the encoding time for ME on CPU. Experimental results demonstrate that the proposed scheme can achieve 41% encoding time savings with the ME acceleration up to 12.7 times, and the incurred BD-BR loss is only 0.52% on average. Moreover, further experimental results show that the proposed GPU-based ME can achieve up to 200 times acceleration compared to the full search ME on CPU.

Optimized Hexagonal Search for Fast Motion Estimation Based on Bees Algorithm

Optimized Hexagonal Search for Fast Motion Estimation Based on Bees Algorithm

Compressed domain zoom motion classification using local tetra patterns

In this paper, a novel compressed domain method for classifying zooming motion is presented. Camera zoom motion classification is an important problem in video analysis wherein the task is to recognize and separate zooming-in camera from zooming-out camera. In our study, we address this problem utilizing local tetra patterns which has earlier found applications in image texture analysis and content-based image retrieval. Towards this goal we model the motion vector orientation and magnitude using local tetra patterns followed by histogram formation. Since the feature dimension is large, uniform pattern-based feature reduction is applied on the histograms to form the feature vector which is fed to the C-SVM classifier for training/testing purposes. Experimental testing utilizing standard video sequences with block motion vectors coming from exhaustive search motion estimation algorithm as well as H.264 obtained block motion vectors along with comparative analysis carried out with existing techniques shows superior performance for the proposed method.

An adaptive hash-based search for integer motion estimation in SCC

An adaptive hash-based search for integer motion estimation in SCC

Novel architecture and implementation of low power oriented full search block motion estimation

High efficient video coding (HEVC) succeeds dual coding efficiency development contrasted to its predecessor H.264/MPEG-4 AVC. Though, it experiences high computational complexity caused by its quad-tree structure in motion estimation (ME). The full search ME (FSME) procedure can fundamentally raise the video encoder compression ratio (CR) while maintaining high video quality, but it is also fundamentally expensive and can comprise of more than 45% of the entire motion estimation method. The consecutive rate-constrained elimination technique (CRCE) safely removes contender motion vectors while saving the best aspirant chosen by the full search block motion estimation (FSBME) method. However, these methods have been failed to consume less power. This paper proposes low power oriented full search block based motion estimation (LP-FSBME) algorithm. The proposed algorithm decomposes every block into subsequent sub-pixel blocks by computing the sum of absolute difference (SAD) values of sub-pixel search locations utilizing the SAD benefits of neighboring integer pixel search areas for best motion vector (MV) and it diminishes the computational complexity. The proposed method hardware design is implemented with Verilog Hardware Description Language (Verilog-HDL) and synthesized by Xilinx Virtex 7 FPGA XC7VX1140T device with speed grade 1 in Xilinx software version 14.5. The proposed method is checked videos occupied 754 K gate counts, 4410 Look Up Tables (LUTs), 3312 Registers, maximum occupied frequency is 204 MHz, maximum power consumption is 40.14 mW in 1080 pixels @ 30 frames per second.

A Novel Search Area Data Reuse Method for Memory Access Optimization of Fast Search Motion Estimation

Motion estimation (ME) is a time-consuming algorithm to find a matching block in the search area for video applications, such as video compression. Motion estimation algorithm includes full search algorithm and fast search algorithm. If the width of the motion estimation algorithm search area is twice the size of the block, half of the search area for adjacent blocks overlaps. In view of this, this paper proposes a search area data reuse method for fast search motion estimation. With the proposed data reuse implementation, only the first block needs to read the data of the entire search area from the off-chip memory. The other blocks only need to read half the original search area. In this way, time of access to external memory is reduced, and running time of the algorithm is also decreased. Experimental results of diamond search show that the search area data reuse methods can reduce the running time by 40% to 60% compared with the algorithm of no use data reuse, and it can also reduce the power consumption by 62% to 73%. Compared with other methods in the literature, the proposed method also performs better on running time and power consumption.

A novel parallel implementation of partial distortion search algorithm based on template search

This paper proposes a new early terminating partial distortion search algorithm based on template search in fast motion estimation. Our algorithm accomplishes a parallel implementation technique by considering both the idea of partial distortion search and the advantage of the template search. With this technique, the proposed algorithm achieves a better performance by faster updating the current minimum distortion. The proposed parallel implementation that reduces a large amount of distortion computations between pixels outperforms the standard partial distortion search method by faster rejecting the unlikely candidate blocks. Our algorithm is embedded into the diamond search algorithm, star diamond search algorithm and three-step search algorithm respectively. According to the experiment results, it is proved that about 30% reduction of computational complexity has been obtained compared with the standard partial distortion search. Moreover, there is no degradation of the peak signal-to-noise ratio(PSNR) for motion estimation compared with the embedded block-based template search motion estimation algorithm.

Algorithm and Architecture Design of Multirate Frame Rate Up-conversion for Ultra-HD LCD Systems

In current liquid crystal display (LCD) systems, the frame size becomes larger than the ultra-HD ( $3840\times 2160$ ) resolution, and the refresh rate becomes higher than 120 Hz or more. However, the available video frame rates are usually at 24, 30, or 60 frames/s only, which are lower than the refresh rate of LCDs. To fill the gap between the video and LCD systems, frame interpolation techniques are usually adopted. Although frame rate up-conversion (FRUC) is regarded as the most efficient method, many design challenges are encountered in the current high-resolution and high-frame-rate LCD systems. In this paper, we developed a hardware-efficient multirate FRUC, which is capable of increasing the video frame rate from 24 or 60 to 120 frames/s. We improved the accuracy of motion vectors (MVs) between the video frames using predictive square search motion estimation (ME), followed by Markov random field (MRF) correction. Subsequently, we applied the block-based forward motion compensation (MC) to interpolate the intermediate frames. Thereafter, we performed subblock refinement to enhance the visual quality. The experiments show that the proposed algorithm performed well in both subjective and objective evaluations. We also designed hardware architecture for our multirate FRUC to support the current ultra-HD LCD systems. We proposed ping-pong two-way scheduling to eliminate the dependence among blocks. We realized 54%, 70%, and 35% cycle reduction and 62%, 82%, and 35% bandwidth reduction in the ME, MRF MV correction, and MC, respectively. The SRAM was shared by all modules, and its total size was reduced by 88%. We also implemented our design to a chip using the TSMC 90-nm cell library.

Adaptive Search Range for HEVC Motion Estimation Based on Depth Information

High Efficiency Video Coding achieves twofold coding efficiency improvement compared with its predecessor H.264/MPEG-4 Advanced Video Coding. However, it suffers from high computational complexity due to its quad-tree structure in motion estimation (ME). This paper exposes the use of depth maps in the multiview video plus depth format for relieving the computational burden. The depth map provides an intimation of the objects' distance from the projected screen in a 3D scene, which is explored in adaptive search range determination in this paper. The proposed algorithm exploits the high temporal correlation between the depth map and the motion in texture. By utilizing this correlation, a depth/motion relationship map is built for a mapping process. For each block, this forms a tailor-made search range with a motion-aware asymmetric shape to skip unnecessary search points in ME. The obtained search range can be further adjusted by taking the influence of 3D-to-2D projection into consideration. Simulation results reveal that, compared to the full search approach, the proposed algorithm can reduce the complexity by 93% on average, whereas the coding efficiency can be maintained. Besides, the proposed search range determination can work well with other fast search ME algorithms in the literature.

An Efficient Block Matching Algorithm for Fast Motion Estimation Using New Three Step Search and Tabu Search Algorithm

Over the last couple of decades, video processing and coding has grown exponentially. The processing power of the computers available has grown in almost equal proportions. However, with the introduction of newer video standards, which are further more complex, it has become imperative to work on more optimized algorithms and implement them efficiently and judiciously. In this paper, we compare the two most commonly used search algorithms, New Three step and Tabu Search for motion estimation and decide which one is better for a given type of video sequence. This information can help in better decision making regarding the choice of the algorithm for a certain video sequence and PSNR improved up to 40.0742.

An improved adaptive selection search for block motion estimation

Motion estimation has an important effect in H.265 video coding systems because it occupies a large amount of time in encoding system. So the quality of motion search selection affects the entire encoding efficiency directly. In this paper, a novel search algorithm which utilises an adaptive hexagon and small diamond search is proposed to overcome the drawbacks of the traditional block matching selection implemented in most current video coding standards. The adaptive search algorithm is chosen according to the motion strength of the current block. When the block is in active motion, the hexagon search provides an efficient search method; when the block is inactive, the small diamond search is adopted. Experimental simulation results showed that our adaptive search algorithm can speed up the search process with little effect on distortion performance compared with other traditional approaches.

An improved adaptive selection search for block motion estimation

Motion estimation has an important effect in H.265 video coding systems because it occupies a large amount of time in encoding system. So the quality of motion search selection affects the entire encoding efficiency directly. In this paper, a novel search algorithm which utilises an adaptive hexagon and small diamond search is proposed to overcome the drawbacks of the traditional block matching selection implemented in most current video coding standards. The adaptive search algorithm is chosen according to the motion strength of the current block. When the block is in active motion, the hexagon search provides an efficient search method; when the block is inactive, the small diamond search is adopted. Experimental simulation results showed that our adaptive search algorithm can speed up the search process with little effect on distortion performance compared with other traditional approaches.

Fast motion estimation algorithm using multilevel distortion search in Walsh–Hadamard domain

Block-matching motion estimation (BME) can efficiently reduce the temporal redundancy between the successive video sequences in video compression coding system. In this study, a fast BME algorithm using multilevel distortion search in Walsh–Hadamard domain is proposed to reduce the computational burden and speed up coding process. First, the proposed algorithm divides the block into several sub-blocks. Then, the Walsh–Hadamard transform is applied to these sub-blocks. Finally, the proposed algorithm calculates the partial block matching distortion by utilising a novel back diagonal search scheme which can quickly reject unnecessary candidate block in a multilevel manner. Experimental results show that the proposed algorithm effectively reduces the number of operations in block distortion calculation meanwhile maintains the best motion estimation matching quality. Compared with the full search, the proposed algorithm can reduce 87.19% computational complexity without any degradation of the peak signal to noise ratio. In addition, compared with the partial distortion search algorithm, successive elimination algorithm, multilevel successive elimination algorithm and the transform-domain successive elimination algorithm, the proposed algorithm can also save 68.27, 70.09, 37.81 and 37.44% computational complexity, respectively. Moreover, the proposed algorithm can also be easily incorporated into any block-based template search motion estimation algorithm.

Search range reduction for uni-prediction and bi-prediction in HEVC

The motion estimation block of the high-efficiency video coding (HEVC) standard is highly complex. This paper proposes two algorithms, namely external search range reduction (ESR) and internal search range reduction (ISR) to reduce the motion estimation complexity of HEVC in uni-prediction and bi-prediction both in the fast search mode. The proposed ESR algorithm for uni-prediction motion estimation reduces the search range adaptively for Test Zonal Search (TZS) motion estimation with negligible loss in coding efficiency. The proposed ISR algorithm for uni-prediction, namely ISR-R, limits the search range further in the raster search stage of the TZS algorithm. Moreover, a fast bi-prediction motion estimation algorithm is proposed which includes both ESR and ISR to reduce the motion estimation complexity in bi-prediction. Our algorithms are implemented in the HM-16.6 encoder in the fast search mode. The performance of the proposed algorithms are tested individually and then by combining all the algorithms. When the algorithms are combined, the number of search points and motion estimation time are reduced by 60.58 and 59.58 %, respectively in the fast search mode with a BD-Rate of 0.193 % and BD-PSNR of −0.005 % in the LD-B main profile. The number of search points and motion estimation time are reduced by 59.55 and 57.71 %, respectively in the fast search mode with a BD-Rate of 0.265 % and BD-PSNR of −0.008 % in the RA main profile.

Adaptive order search and tangent-weighted trade-off for motion estimation in H.264

Motion estimation and compensation play a major role in video compression to reduce the temporal redundancies of the input videos. A variety of block search patterns have been developed for matching the blocks with reduced computational complexity, without affecting the visual quality. In this paper, block motion estimation is achieved through integrating the square as well as the hexagonal search patterns with adaptive order. The proposed algorithm is called, AOSH (Adaptive Order Square Hexagonal Search) algorithm, and it finds the best matching block with a reduced number of search points. The searching function is formulated as a trade-off criterion here. Hence, the tangent-weighted function is newly developed to evaluate the matching point. The proposed AOSH search algorithm and the tangent-weighted trade-off criterion are effectively applied to the block estimation process to enhance the visual quality and the compression performance. The proposed method is validated using three videos namely, football, garden and tennis. The quantitative performance of the proposed method and the existing methods is analysed using the Structural SImilarity Index (SSIM) and the Peak Signal to Noise Ratio (PSNR). The results prove that the proposed method offers good visual quality than the existing methods.

Constructive Synthesis of Memory-Intensive Accelerators for FPGA From Nested Loop Kernels

Field-programmable gate arrays are ideal hosts to custom accelerators for signal, image, and data processing but demand manual register transfer level design if high performance and low cost are desired. High-level synthesis reduces this design burden but requires manual design of complex on-chip and off-chip memory architectures, a major limitation in applications such as video processing. This paper presents an approach to resolve this shortcoming. A constructive process is described that can derive such accelerators, including on- and off-chip memory storage from a C description such that a user-defined throughput constraint is met. By employing a novel statement-oriented approach, dataflow intermediate models are derived and used to support simple approaches for on-/off-chip buffer partitioning, derivation of custom on-chip memory hierarchies and architecture transformation to ensure user-defined throughput constraints are met with minimum cost. When applied to accelerators for full search motion estimation, matrix multiplication, Sobel edge detection, and fast Fourier transform, it is shown how real-time performance up to an order of magnitude in advance of existing commercial HLS tools is enabled whilst including all requisite memory infrastructure. Further, optimizations are presented that reduce the on-chip buffer capacity and physical resource cost by up to 96% and 75%, respectively, whilst maintaining real-time performance.