Novel architecture and implementation of low power oriented full search block motion estimation

Abstract

High efficient video coding (HEVC) succeeds dual coding efficiency development contrasted to its predecessor H.264/MPEG-4 AVC. Though, it experiences high computational complexity caused by its quad-tree structure in motion estimation (ME). The full search ME (FSME) procedure can fundamentally raise the video encoder compression ratio (CR) while maintaining high video quality, but it is also fundamentally expensive and can comprise of more than 45% of the entire motion estimation method. The consecutive rate-constrained elimination technique (CRCE) safely removes contender motion vectors while saving the best aspirant chosen by the full search block motion estimation (FSBME) method. However, these methods have been failed to consume less power. This paper proposes low power oriented full search block based motion estimation (LP-FSBME) algorithm. The proposed algorithm decomposes every block into subsequent sub-pixel blocks by computing the sum of absolute difference (SAD) values of sub-pixel search locations utilizing the SAD benefits of neighboring integer pixel search areas for best motion vector (MV) and it diminishes the computational complexity. The proposed method hardware design is implemented with Verilog Hardware Description Language (Verilog-HDL) and synthesized by Xilinx Virtex 7 FPGA XC7VX1140T device with speed grade 1 in Xilinx software version 14.5. The proposed method is checked videos occupied 754 K gate counts, 4410 Look Up Tables (LUTs), 3312 Registers, maximum occupied frequency is 204 MHz, maximum power consumption is 40.14 mW in 1080 pixels @ 30 frames per second.