Schematic Level Research Articles

Withdrawal: P. A. Harsha Vardhini and M. Makkena (2022), Design and Comparative Analysis of On‐Chip Sigma Delta ADC for Signal Processing Applications. Advanced Control for Applications: Engineering and Industrial Systems. Accepted Author Manuscript e82. https://doi.org/10.1002/adc2.82

Advent in VLSI technology made digital signal processing to take over analog signal processing. Analog to digital converter plays a vital role in modern digital processing applications. Sigma delta analog to digital converter architecture being digital dominant architecture is much suitable for signal processing applications. This paper presents the design of a low pass continuous time sigma delta analog to digital converter on-chip architecture suitable for signal processing applications with a very few passive components connected externally to FPGA. Schematic level architecture of high-speed comparator working at a differential swing which is not allowed by standard differential pads is designed. By applying various differential swings at the input to LVPECL, the performance and power is analyzed. High performance comparator schematic is designed for On-chip Continuous-time Sigma-delta ADC architecture. Simulations are carried out to verify the maximum input frequency for given RC values. Xilinx provided Spartan 6 I/O pad and package SPICE models are used. Power analysis is carried out with LVPECL logic family based differential buffers along with external RC circuit. The analog and digital sections simulations along with mixed signal simulations at different stages are performed. Power and performance analysis are carried out using H-Spice and Questasim simulations.

A new CMOS compatible high performance first-order all-pass filter realisation

ABSTRACT A new realisation of an electronically tunable first-order voltage-mode all-pass filter enjoying the feature of low voltage and low power is proposed in this paper. The proposed realisation of filter employs only one active element namely differential voltage extra-x current controlled conveyor and one grounded capacitor. The use of minimal number of components makes the proposed structure simple and attractive from chip fabrication point of view. The performance of proposed structure is also discussed by considering the effects of parasitic and non-idealities of the used active element. Additionally, higher order filter realisation is also included to enrich the presented work by exploring possible applicability aspects. The theoretical performance is validated at schematic level using 0.18 µm CMOS technology parameters with ±1 V supply voltages. Furthermore, Cadence Analog Design Environment (ADE) with gpdk 0.18 µm technology is used to design the layout of the proposed circuit. Pre-layout and post-layout simulation verification is provided to extend the real time validation of theoretical aspects.

Metaphors and trauma: An image schematic analysis of symptom-specific metaphors

Metaphor analysis is known to be insightful for understanding how psychological trauma is conceptualized. While previous research on trauma metaphors mainly examined the subjective experience of general traumatic feelings, little has been said about post-traumatic symptoms of clinical significance. This paper investigates symptom-specific metaphors produced by five trauma victims, who were exposed to the 2019–2020 social unrest in Hong Kong and met the diagnostic criteria of Acute Stress Disorder (ASD) as assessed by the Stanford Acute Stress Reaction Questionnaire (SASRQ). Sixty-four symptom-specific metaphors were categorized according to the post-traumatic symptoms they described and examined for their image schematic groundings. Although the participants had no professional knowledge about post-traumatic symptoms, they still described the feelings using experientially distinct constructs. The findings reveal the possibility for symptomatological manifestations to be captured in metaphorical language and distinguished at the image schematic level, highlighting the complementary value of symptom-level analysis in cognitive semantic analysis of trauma metaphors.

A na\xefve HMO study of the casimir effect

The Casimir effect is discussed via an HMO treatment. At this schematic theoretical level, the Casimir effect might be considered as the result of the general quantum mechanical interaction behavior of two sets of particles.

Extraction of Single Cell Impedance From Battery Module Measurement by Simulation-Based De-Embedding

Batteries are a fundamental part of many modern electric systems. As a result, battery modeling is increasingly important for the prediction of signal and power integrity (SIPI) as well as electromagnetic compatibility (EMC). Conventional battery module modeling requires knowledge of the integrated cells first, which is usually obtained by measurement on single cells. However, if individual cells are not accessible, the single cell's impedance needs to be extracted from measurement of the complete module. This work describes two solutions to this problem, which are both based on 3D electromagnetic (EM) simulation of the battery module with surrogate cell models to obtain S-parameters which describe coupling effects inherent to the modules's geometry. By either fitting of the simulated module impedance to the measured data on circuit schematic level, or by numerical multiport de-embedding, the single cell impedance is extracted. Considered frequencies range from 9 kHz to 1 GHz.

Book Review. A New Insight into Theory of Conceptual Metaphor

Book Review. A New Insight into Theory of Conceptual Metaphor

Revisiting what is termed as Anomalous Formulaic Expressions in the Qur'anic Discourse: A Cognitive Study from a Pragma-Stylistic Perspective

Abstract: This cognitive, small-scale study reviews the formulaic expressions used in the Quranic discourse. From a pragma-stylistic view, it examines the extent to which the Quranic expressions identified by Arab linguists as ‘odd’ words are used as discourse markers. Based on more recent denotational theories, the paper claims that these expressions are unlikely to be anomalous. It theorizes that these phrases are verbal clues that work on the discourse level. The study utilizes corpus linguistics for data collection. Theoretically, it builds on discourse analysis (DA) as a main approach to data categorization and analysis. Thus, it models on Fairclough (2013) and Van Dijk's (1998) analytical framework to describe, interpret and explain the senses of these expressions in the various processes of meaning production, consumption and realization. A systematic, linguistic analysis is carried out on the syntactic, semantic and schematic levels. It has been found that these expressions fit into some formulaic sequences in which the components refer either directly to the discourse or indirectly to the context in which the embolic term is used. The contexts in which the formulaic patterns are selected and used are mainly characterized by hypersensitivity to sex and abstractedness of comprehension. The linguistic features of the expressions suggest that the Quranic discourse uses them for language politeness to keep face, for more linguistic interactions to clarify meaning and for hedging to sustain other potential senses. Finally, the study implicates for research on pragmatic and translation studies.

Design Flow for Hybrid CMOS/Memristor Systems—Part I: Modeling and Verification Steps

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

BRILLIANT, SUNNY AND BRIGHT: GENERALISED IINVARIANCE THROUGH ETYMOLOGY

The relevance of image schemas in metaphoric extension has been long highlighted in Cognitive Linguistics literature. The image-schematic makeup of a metaphoric source is preserved in the target, in a way consistent with the structure of the latter (Lakoff, 1993). More recently, Sullivan (2013) has raised a similar case for semantic frames, in a constructional framework. Metaphoric mappings are licensed only if the semantic frame of the source is compatible with the conceptual metaphor profiled by the target. The present work integrates Sullivan and Lakoff’s approach to invariance, on the basis of the following hypothesis: the compatibility between a semantic frame evoked by a lexical construction and a conceptual metaphor is susceptible to an imageschematic blueprint, already present in the etymologically prior meaning of the construction. Thus, invariance is hypothesised to hold across categorisation levels of different schematicity, but also across time. The case study re-takes the analysis of the adjectival terms brilliant, sunny and bright, under the generalised invariance hypothesis. The metaphorical potential of a term is shown to be at the same time constrained as well as motivated by this strong version of invariance.

FinFET based Design and Performance Analysis of Nano-processor for Low Area, Low Power and Minimum Delay using 32nm

The recent technologies in VLSI chips has grown in terms of scaling of transistor and device parameters but still there is a challenging task for controlling of current between source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip manufacturing, through which current can be effectively controlled. This section addresses the issues present in CMOS technology and majorly concentrated on proposed 4-bit Nano processor using FinFET 32nm technology by using Cadence Virtuoso software tool. In the proposed Nanoprocessor design, the first portion of the design is done using 4bit ALU which includes all basic and universal gates, high speed adder, multiplier and multiplexer. The Carry Save Adder (CSA) and multiplier are the major sub component which can optimize the power consumption and area reduction. The second portion of the proposed Nano processor design is 4-bit 6T SRAM and encoder and decoder and also using Artificial Neural Network (ANN). All these sub components are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS and at the last chip level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET using technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% with optimization in power dissipation of 47% along with optimization in leakage current, with 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses are compressed subsequently respectively. The basic gates, universal gates, CSA, subtraction and MUX are integrated for 4-bit ALU design and its delay, power consumption and area are found to be 0.104nsec, 314.4uW and 56.8μsqm respectively.

Assessing the impact of syntactic complement type on the modifying status of complement-taking predicates: the case of imagine

The present study examines the grammaticalization potential of different syntactic complement types by means of a case study of the complement-taking predicate (CTP) imagine. Building on the assumption that CTP-clauses can be conceived of as embedded within a larger taxonomy of interrelated constructions at various levels of schematicity, it is argued that the development of grammatical variants with one complement type should also be viewed in relation to other complementation patterns realized by that predicate. Similarities and differences between complementation types were visualized by means of a hierarchical cluster analysis of 2000 instances of imagine from the Spoken BNC2014 corpus. It is shown that there is a distribution of labor between the complement types in terms of the structure and semantics of their respective CTP-clauses. Qualitative analyses furthermore confirm that only CTP-clauses with zero complementation meet all criteria for grammatical status, although interpersonal functions can also be found with other syntactic complement types. The exploitation of this interpersonal function, it is argued, may eventually also result in the grammaticalization of more formulaic units with imagine.

First principle calculations of structural and electronic properties of pyrochlore Y2Ru2O7 and Y1-xMxRu2O7−δ (M=Mg, Ca, Sr, Ba, Zn, Cd and Hg)

The electronic structural and electronic properties of pyrochlore Y2Ru2O7 (YRO) and Y1-xMxRu2O7−δ (M = Mg, Ca, Sr, Ba, Zn, Cd and Hg) were investigated using first-principle calculation based on GGA + U and HSE06 hybrid functional. The schematic energy level diagram of YRO was drawn, and its band gap was found to locate in π* antibonding orbital, dominated by Ru-4d electrons. RuO6 octahedrons in YRO undergo a compressing trigonal distortion, with a local symmetry group of D3d, which is quite different from RuO2 and perovskite ruthenium oxide. When Y is substituted by divalent cation M (MY), O vacancies can achieve low formation energy and introduce the MY-VO and 2MY-VO complex. Further calculation showed that MY-VO complex in YRO can induce an impurity energy level into forbidden band, and narrow the band gap. As a result, high electrical conductivity of Y1-xMxRu2O7−δ is expected, and MY-VO complex may be the origin of electrocatalytic activity in Y1-xMxRu2O7.

An aspectual contour of phrasal verb constructions with English think

Abstract In English, the internal constituency of an event is obligatorily expressed by means of non-progressive versus progressive aspect. It is also represented linguistically by means of lexical aspect, and thus verb semantics. The two types of distinctions are shown to lie at two different levels of schematicity in the Integrated Model of Aspect (IMA, Kokorniak 2018). Although particles constitute only an additional tool in aspectual profiling in English, they are very productive at the level of lexical aspect in profiling minor aspectual differences that main verb semantics and inflection cannot reflect. The particles that the verb think can be combined with include out, over, through and up. Monolingual learners’ dictionaries suggest that think out, think over and think through can be used interchangeably. Their definitions indicate that in all three cases the particles designate a careful and thorough mental process. The study presents an aspectual contour of think and the particles that the verb can be combined with, and displays that each particle constitutes an elaboration of the mental path in a slightly different way. Their semantic contribution to the aspectual verb profile is shown and located in the IMA continuum, while corpus examples depict their use.

Naphthalenothiophene imide-based polymer exhibiting over 17% efficiency

Summary Developing novel electron-deficient monomers is crucially important for the future development of non-fullerene organic solar cells. Here, we report a new electron-deficient monomer naphthalenothiophene imide (NTI) and NTI-based copolymers PNTB and PNTB-2T. The strong electron-withdrawing ability of NTI could effectively lower the HOMO level of the polymer that facilitates the tuning of the polymer’s physical properties while simultaneously maintaining the low-lying HOMO value. Polymer chains modification by introducing extra thiophenes results in the closed π−π stacking and ordered polymer chain packing of PNTB-2T and is proven to be an effective strategy to increase the device performance. Thus, solar cell devices for PNTB-2T:Y6 exhibit an efficiency of 16.72%, which is further enhanced to 17.35% by the third component PC71BM, whereas that for PNTB:Y6 is only 3.81%. Importantly, PNTB-2T-based devices exhibit excellent batch-to-batch reproducibility. These features make this family of polymer donors very promising and the design strategies will enlighten future development of high-performance polymer donors for organic solar cells (OSC).

Quenching of the Eu3+ Luminescence by Cu2+ Ions in the Nanosized Hydroxyapatite Designed for Future Bio-Detection.

The hydroxyapatite nanopowders of the Eu3+-doped, Cu2+-doped, and Eu3+/Cu2+-co-doped Ca10(PO4)6(OH)2 were prepared by a microwave-assisted hydrothermal method. The structural and morphological properties of the products were investigated by X-ray powder diffraction (XRD), transmission electron microscopy techniques (TEM), and infrared spectroscopy (FT-IR). The average crystal size and the unit cell parameters were calculated by a Rietveld refinement tool. The absorption, emission excitation, emission, and luminescence decay time were recorded and studied in detail. The 5D0 → 7F2 transition is the most intense transition. The Eu3+ ions occupied two independent crystallographic sites in these materials exhibited in emission spectra: one Ca(1) site with C3 symmetry and one Ca(2) sites with Cs symmetry. The Eu3+ emission is strongly quenched by Cu2+ ions, and the luminescence decay time is much shorter in the case of Eu3+/Cu2+ co-doped materials than in Eu3+-doped materials. The luminescence quenching mechanism as well as the schematic energy level diagram showing the Eu3+ emission quenching mechanism using Cu2+ ions are proposed. The electron paramagnetic resonance (EPR) technique revealed the existence of at least two different coordination environments for copper(II) ion.

Design and comparative analysis of on-chip sigma delta ADC for signal processing applications

Advent in VLSI technology made digital signal processing to take over analog signal processing. Analog to digital converter plays a vital role in modern digital signal processing applications. Various signal processing applications incorporated sigma delta ADC among different analog to digital converters because of its digital dominant architecture. This paper presents the design of a low pass continuous time sigma delta analog to digital converter on-chip architecture with a very few passive components connected externally to FPGA suitable for signal processing applications, wireless application, sonar and radar beamforming. Schematic level architecture of high speed comparator working at a differential swing which is not allowed by FPGA standard differential pads is designed. By applying various differential swings at the input to LVPECL, the performance and power is analyzed. High performance comparator schematic is designed as on-chip continuous-time sigma-delta analog to digital converter architecture. SPICE simulations are carried out to verify the maximum input frequency for given RC values. Xilinx provided Spartan 6 I/O pad and package SPICE models are used. Power analysis is carried out with LVPECL logic family based differential buffers along with external RC circuit. The analog and digital sections simulations along with mixed signal simulations at different stages are performed. Power and performance analysis are carried out using h-Spice and questasim simulations. schematic level architecture of a high speed comparator at a differential swing of 1.65 ± 1.5 V which is not allowed by standard differential pads is designed. Analysis illustrates that proposed on-chip continuous-time sigma-delta analog to digital converter exhibits a sampling rate of 400 MHz designed with high speed comparator with varied differential swing. Power analysis resulted with 1.86 mW for an input signal of 1 MHz. Optimal filtering is achieved with total decimation of 400, out of which the decimation of 100 is achieved by CIC filter and PFIR filter achieves remaining decimation factor of 4. Output data rate of 1 MHz with a dynamic range of 72 dB is achieved with less bill of material that suites for signal processing applications.

Design and Performance Analysis of 4-bit Nano-processor Design for Low Area, Low Power and Minimum Delay Using 32nm FinFET Technology

The recent technologies in VLSI Chips have grown in terms of scaling of transistor and device parameters but still, there is challenging task for controlling current between the source and drain terminals. For effective control of device current, the FinFET transistors have come into VLSI chip, through which current can be controlled effectively. This paper is to address the issues present in CMOS technology and majorly concentrated on the proposed 4-bit Nano processor using FinFET 32nm technology by using the Cadence Virtuoso software tool. In the proposed Nano processor, the first part is to design using 4bit ALU which includes all basic and universal gates, efficient and high-speed adder, multiplier, and multiplexer. The Carry Save Adder (CSA) and multiplier are the major subcomponents which can optimize the power consumption and area reduction. The second part of the proposed Nano processor is 4-bit 6T SRAM and Encoder and decoder and also Artificial Neural Network (ANN). All these subcomponents are designed at analog transistors (Schematic level) through which the Graphic Data System (GDS-II) is generated through mask layout design. Finally, the verification and validation are done using DRC and LVS, at the last chip-level circuit is generated for chip fabrication. The ALU is designed by using CMOS inverters and the designed ALU schematic is simulated through 32nm FinFET technological library and compared with CMOS technology which is simulated through 32nm CMOS library (without FinFET). The power consumption of AND, OR, XOR, NOT, NAND gates, SRAM, Encoder, Decoder and ANN are 36.09nW, 64.970nW, 61.13nW, 33.31nW, 37.45nW, 32.5% optimization in power dissipation and 47% optimization in leakage current, 2.68uW, 1.98uW and 7.5% improvement in power consumption and 0.5% information loses compressed subsequently respectively. The basic gates and universal gates, CSA, subtraction, and MUX are integrated for 4-bit ALU design, and its delay, power consumption, and area are 0.104nsec, 314.4uW, and 56.8usqm respectively

Construction mining

Abstract The German Constructicon Project (www.german-constructicon.de) aims at documenting grammatical constructions in contemporary standard German on the basis of annotated corpus examples, including relations between constructions and between constructions and evoked semantic frames. So far, the research focus has been mainly on the development and computational implementation of a constructicographic workflow (including a parsing pipeline) that allows for addressing any kind of constructions on varying levels of schematicity, idiomaticity, and abstractness. However, such an exemplar-driven procedure precludes us from systematically identifying constructional candidates. In this article, we scrutinize ways to operationalize and implement data-mining procedures to inductively identify construction candidates.

WITHDRAWN: Performance analysis and design of finfet 32 nm based low power, low delay 4-bit alu, carry save adder and multiplier for high speed processors

Abstract The limitations of CMOS technology are short channel effects, battery powered problem, power dissipation, delay. All digital circuits like logical and arithmetic operations are performed and designed using CMOS. The power dissipation/consumption in such circuits are more so the fast growing technology requires the lower power dissipation/consumption, low leakage currents and lessor short channel effects. Therefore, to address these issues, the proposed research work has introduced FinFET 32 nm technology for the designing of logical operation, arithmetic, multiplexer, 4-bit ALU, Carry Save Adder (CSA) and multiplier using Cadence Virtuosos software tool. Another challenge in CMOS technology is, size of the transistor which is used to measure area, therefore the proposed research work, optimize the delay, power, W/L ratio and also no of transistors for designing of both gates and arithmetic operations. The work has been carried out from schematic level to layout design to Graphic Data System (GDS II) generation. To validate the FinFET based ALU and multiplier, its detailed analysis of the constraints related to FinFET transistor level and benefits, in which each transistor is modified for the delay at different timings arcs and power consumption, are done. The individual gate and arithmetic operations are tested and calculated in which the delay and power consumption are compared with existing work and it is found that the reduction in the power level for AND, XOR, OR, NAND, NOT gates, full adder, CSA, 2bit multiplier and ALU are 36.09 nW, 61.13nW, 64.97nW, 37.45nW, 33.31nW, 38.22nW, 2.39 μW, 39.89nW and 314.4 μW respectively.

The role of CuO as limiting and luminescent probe for orange red emission of Sm3+ ions in strontium bismuth borosilicate glasses

The properties of glass materials with CuO are suitable for both optical and photovoltaic applications. The role of CuO hinges on the structural properties of glass network. The structural and luminescence properties of melt quenched strontium bismuth borosilicate glasses containing Sm 2 O 3 with varying amounts of CuO (referred as N: SmCu) were studied. Two valence states of Cu ions are possible due to more amount of silica in glass. The amorphous nature of glass was confirmed by XRD and thermal parameters were explained through DTA curves. FTIR spectrum indicated the variation of asymmetric vibrations of SiO 4 units with change in SrO and CuO concentration which influence the valence state of Cu 2+ . The absorption spectra have shown peaks due to 3 d 10 →3 d 9 4s 1 transition of Cu + ions, 6 H 5/2 → 6 P 3/2 transition of Sm 3+ and broad 2 B 1g → 2 B 2g transitions of Cu 2+ ions. The NIR region has peaks of Sm 3+ ions. The Photo Luminescence (PL) spectra of N: SmCu glasses exhibited cyan bluish emission at 485 nm followed by intense emission peaks of Sm 3+ at 312 nm excitation. The emission of N: SmCu10 and N: SmCu12 glasses are quenched due to Cu 2+ ions. Moreover, maximum range of emission is exhibited by ‘N: SmCu8’ glass. The shortening of life time decay observed in ‘N: SmCu’ glasses was inferred to the process of energy transfer. The profiles of life time decay curves are fitted with the help of bi-exponential function. The CIE and CCT values of all glasses are calculated. The white light emission is quite possible in N: SmCu10 glass and the remaining glasses covered Orange - red regions with CCT values ranging from 1892 K–2351 K. The schematic energy level diagram of N: SmCu glasses. • Sm 3+ /Cu 2+ co-doped glasses prepared by melt quench technique. • FTIR show different units of vibrations and DTA profile shows thermal stability. • PL, spectral overlap and life time decay confirms energy transfer. • CIE and CCT value shows white light emission.