Scheduling Window Research Articles

Due window scheduling with sequence-dependent setup on parallel machines using three hybrid metaheuristic algorithms

Due-date determination problems have gained significant attention in recent years due to the industrial focus in the just-in-time philosophy. This paper considers a machine scheduling problem where jobs should be completed at times as close as possible to their respective due dates, and hence, both earliness and tardiness should be penalized. It is assumed that earliness and tardiness (ET) penalties will not occur if a job is completed within the due window. However, ET penalties will occur if a job is completed outside the due window. The objective is to determine a schedule that minimizes sum of the earliness and tardiness of jobs. To achieve this objective, three hybrid metaheuristics are proposed. The first metaheuristic is a hybrid algorithm which combines elements from both simulated annealing (SA) as constructive heuristic search and a variable neighborhood search (VNS) as local search improvement technique. The second one presents a hybrid metaheuristic algorithm which composed of a population generation method based on an ant colony optimization (ACO) and a VNS to improve the population. Finally, a hybrid metaheuristic approach is proposed which integrates several features from ACO, SA, and VNS in a new configurable scheduling algorithm. A design of experiments approach is employed to calibrate the parameters and operators of the algorithm. Computational experiments conducting on 252 randomly generated problems compare the results with the VNS algorithm proposed previously and show that the procedure is capable of producing consistently good results.

Streamlining long latency instructions for seamlessly combined out-of-order and in-order execution

In the current day wide-issue processors, the size of the instruction scheduling window (also called Issue Queue (IQ)) is limited mainly by the hardware complexity to design the logic, and thus limits the number of instructions scanned every cycle to extract instruction level parallelism (ILP). To exacerbate the problems, instructions depending on long latency load operations continue to reside in the IQ until their source operands are ready. Thus, such delayed instructions block any new instructions from entering the IQ even if potentially they are ready for execution. The growing disparity in processor and memory speeds is further aggravating the delay in dislodging instructions from IQ. To alleviate the problem, in this paper we propose a novel technique to streamline instructions in separate buffers according to the chain of dependencies. Each instruction is streamlined behind a parent instruction while it waits for the source operand to be supplied by the long latency memory operations. These instructions are segregated from the IQ and thus the pressure on IQ is relieved which enables flow of potentially executable instructions in the pipeline. Our analysis of SPEC2000 programs reveals that instructions dependent on load cache misses or their dependents, typically have their first source operand ready within 5–15% of their total wait time in the IQ. Based on the observations, the long latency memory dependent instructions are streamlined into in-order buffers when their first operand is ready. In the proposed architecture, instructions from both the conventional IQ and the heads of the streamline buffers can be selected for execution, while the wakeup logic complexity remains same as in the conventional design. Our results show that the performance speedup of 32-entry IQ supplemented by 32 in-order buffers is 15.7% and 2% for FP and integer benchmark respectively, which is very much comparable to that of a conventional 64-entry IQ. A 64-entry IQ design can gain performance over a 32-entry IQ, albeit with a large overhead in circuit delay complexity of wakeup logic, while streamline buffers can gain performance over 32-entry IQ without any such overhead.

Unbounded batch scheduling with a common due window on a single machine*

The common due window scheduling problem with batching on a single machine is dealt with to minimize the total penalty of weighted earliness and tardiness. In this paper it is assumed that a job incurs no penalty as long as it is completed within the common due window. It is the first time for the due window scheduling to be extended to this situation so that jobs can be processed in batches. An unbounded version of batch scheduling is also considered. Hence, jobs, no matter how many there are, can be processed in a batch once the machine is free. For two cases that the location of due window is either a decision variable or a given parameter, polynomial algorithms are proposed based on several optimal properties.

A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance

A scalable, distributed, processor architecture is presented that emphasizes on high performance computing for digital signal processing applications by combining high frequency design techniques w...

Using an operand file to save energy and to decouple commit resources

The register file of a modern superscalar processor is a critical component of the processor pipeline that can have a large impact on processor performance. Large register files provide larger windows of speculation to the processor and allow greater levels of instruction-level parallelism. However, the access time and energy consumption of these structures can grow quite large when these structures increase in size, especially considering the number of ports required. The paper proposes an architecture that moves the large register file needed to fully exploit greater levels of instruction level parallelism off the schedule to the execute path of the processor. This is accomplished by decoupling the instruction window (the amount of instruction state maintained in the reorder buffer and register file) from the scheduling window (the working set of registers required by the instruction scheduler and execution core). The state of the scheduling window is maintained by an operand file and a speculative logical register file. The operand file stores only the set of input registers to be consumed by instructions in the issue queue, and provides low-latency and energy efficient storage for the working set of registers. This design can reduce the energy dissipation by a factor of 6.5 on average over a traditional large register file, and allows the instruction window to be scaled independently of the register file structures on the schedule to execute path.

Effect of hysteroscopy performed in the cycle preceding controlled ovarian hyperstimulation on the outcome of in vitro fertilization

Effect of hysteroscopy performed in the cycle preceding controlled ovarian hyperstimulation on the outcome of in vitro fertilization

Scheduling hospital services: the efficacy of elective-surgery quotas

We take advantage of the advance-scheduling property for elective surgeries by exploring whether the use of a daily quota system with a 1-week or 2-week scheduling window would improve the performance of a typical intensive care unit (ICU) that serves patients coming from a number of different sources within the hospital. The exploration is carried out via a simulation model whose parameters are established from actual ICU data that were gathered over a 6-month period. It is shown that formally linking one controllable upstream process, namely the scheduling of elective surgeries through a quota system, to the downstream ICU admission process, can have beneficial effects throughout the hospital.

Dynamic Dispatching of Cyclic Real-Time Tasks with RelativeTiming Constraints

In some hard real-time systems, relative timing constraints may be imposed on task executions, in addition to the release time and deadline constraints. Relative timing constraints such as separation or relative deadline constraints may be given between start or finish times of tasks (Gerber et al., 1995; Han and Lin, 1989; Han et al., 1992; Han and Lin, 1992; Han et al., 1996). One approach in real-time scheduling is to find a total order on a set of N tasks in a scheduling window, and cyclically use this order at run time to execute tasks. However, in the presence of relative timing constraints, if the task execution times are nondeterministic with defined lower and upper bounds, it is not always possible to statically assign task start times at pre-runtime for a given task ordering (Gerber et al., 1995). We develop a technique called dynamic cyclic dispatching as an extension of a parametric dispatching mechanism in (Gerber et al., 1995). An ordered set of N tasks is assumed to be given in a scheduling window and this schedule(ordering) is cyclically repeated at runtime in consecutive scheduling windows. Relative timing constraints between tasks may be defined across scheduling window boundaries as well as within one scheduling window. A task set is defined to be dispatchable if there exists any way in which the tasks can be dispatched with all their timing constraints satisfied. An off-line algorithm is presented to check the dispatchability of a task set and to obtain parametric lower and upper bound functions for task start times if the task set is dispatchable. These parametric bound functions are evaluated at runtime to obtain a valid time interval during which a task can be started. The complexity of this off-line component is shown to be O(n^2N^3) where n is the number of tasks in a scheduling window that have relative timing constraints with tasks in the next scheduling window. An online algorithm can evaluate these bounds in O(N) time. Unlike static approaches which assign fixed start times to tasks in the scheduling window, our approach allows us to flexibly manage the slack times at runtime without sacrificing the dispatchability of tasks. Also, a wider class of relative timing constraints can be imposed to the task set compared to the traditional approaches.

NN based ATM cell scheduling with queue length-based priority scheme

The asynchronous transfer mode (ATM) is the choice of transport mode for broadband integrated service digital networks (B-ISDNs). We propose a window-based contention resolution algorithm to achieve higher throughput for nonblocking switches in ATM environments. In a nonblocking switch with input queues, significant loss of throughput can occur due to head-of-line (HOL) blocking when first-in first-out (FIFO) queueing is employed. To resolve this problem, we employ bypass queueing and present a cell scheduling algorithm which maximizes the switch throughput. We also employ a queue length based priority scheme to reduce the cell delay variations and cell loss probabilities. With the employed priority scheme, the variance of cell delay is also significantly reduced under nonuniform traffic, resulting in lower cell loss rates (CLRs) at a given buffer size. As the cell scheduling controller, we propose a neural network (NN) model which uses a high degree of parallelism. Due to higher switch throughput achieved with our cell scheduling, the cell loss probabilities and the buffer sizes necessary to guarantee a given CLR become smaller than those of other approaches based on sequential input window scheduling or output queueing.

A NOTE ON “COMMON DUE WINDOW SCHEDULING”

Kramer and Lee recently addressed a common due window scheduling problem with earliness and tardiness penalties, where earliness and tardiness penalty factors are constant and the common window size is given. They showed that the problem is polynomial when the location of the due window is a decision variable. For the case where the location of the due window is given, the problem is also polynomial when the latest due date is greater than or equal to the makespan, and they proposed a pseudopolynomial dynamic programming algorithm to find an optimal schedule when the latest due date is less than the makespan. In this note we address the problem for the case where the location of the due window is given. Specifically, we show that the problem is polynomial if the window location is unrestricted, and present a more efficient dynamic program algorithm to optimally solve the problem if the window location is restricted. The concepts of unrestricted and restricted window locations are defined in this note.

A time-sensitive object model for real-time systems

Process-oriented models for real-time systems focus on the timing constraints of processes , a focus that can adversely affect resulting designs. Data dependencies between processes create scheduling interactions that limit the times at which processes may execute. Processes are then designed to fit available windows in the overall system schedule. “Fitting in” frequently involves fragmenting processes to fit scheduling windows and/or designing program and data structures for speed rather than for program comprehension. The result is often a system with very sensitive timing that is hard to understand and maintain. As an alternative to process-oriented design, we present time-sensitive objects: a data-oriented model for real-time systems. The time-sensitive object (TSO) model structures systems as time-constrained data, rather than time constrained processing. Object values are extended to object histories in which a sequence of time constrained values describe the evolution of the object over time. Systems comprise a set of objects and their dependencies. The TSO model describes the effects of object operations and the propagation of change among related objects. Periodic objects, a class of objects within the TSO model, are described in detail in this article and compared with traditional periodic processes. Advantages of time-sensitive objects are identified, including greater scheduling independence when processes have data dependencies, more opportunity for concurrency, and greater inherent capability for detection of and tolerance to timing errors.

Due window scheduling for parallel machines

Just-In-Time concepts are of increasing importance in today's competitive manufacturing environment. Concerning problem settings with earliness and tardiness penalties, researchers have studied a variety of problems where jobs incur no penalty for completion at a certain point in time. In practice, however, a job completion is acceptable without penalty rather for a time interval, which we call due window. We therefore extend recent work concerning due window scheduling from the single machine case to the parallel machine case. We show that even the unit weight case is NP-complete for parallel machines, provide a dynamic programming algorithm for the two machine case as well as a heuristic with absolute error bound. The heuristic and its error bound are extended to the general case. As the number of jobs increase, the relative error bound vanishes.

A register window scheduling method for prolog

Abstract This paper describes a windowed register file management technique for Prolog that we call “SORWT'’ (Splittable Overlapped Register Window Technique). This scheme is implemented in our Prolog system. Two pointers, the CWP (Current Window Pointer) and TWP (Top Window Pointer), are used with the register file so that the environment, choice point and arguments can be stored in register windows. This greatly reduces the number of memory accesses and procedure call/return overhead. This paper describes in detail how Warren instructions can be implemented in a windowed register file system. A mapping function between register windows and memory window areas and register file overflow/underflow handling algorithms are also presented. In addition, to cope with argument overflow problems in a window, the concept of extended windows is proposed. Thirty benchmark programs are used to study the following effects: performance issue of SORW versus conventional stacked register windows; optimal register file and window sizes; argument overflow rate; and the efficiency of extended windows.

A robust broadband headend switching algorithm

Local area networks (LANs) with a branching rooted-tree topology are considered. In these systems, the metropolitan area gateway (MAG) is responsible for coordinating the flow of traffic into and out of the local subnetworks. A traffic scheduling technique is proposed for this topology. The algorithm is motivated by a finite-horizon maximization of conditional channel cycle utilization, resulting in a zero/infinite scheduling window scheme. Improved mean delay performance is achieved over a much wider range of traffic conditions than for other known algorithms. In order to obtain this robust behaviour, the local media access algorithms are modified to interact with the dynamic scheduling scheme in the MAG. >

A Scheduling Strategy for a Distributed Hard Real-Time Programming Environment

Abstract In this paper we discuss the integrated scheduling strategy adopted to try to met the timing requirements of distributed programs written in STER. Programs in STER include periodic modules (or tasks) with precedence relations, aperiodic modules and modules without timing requirements (non real-time modules). Modules can share remote resources using servers. A client module can access a server using single service requests or multiservice accesses. In a multiservice access a server is allocated in exclusive mode to the client for a given sequence of service requests. The scheduling strategy discussed in this paper consists of three levels: off-line scheduling of periodic modules and on-line scheduling of aperiodic and non real-time modules. To off-line search for a feasible schedule, a known heuristic algorithm was extended to support the concepts of module, server and multiservice accesses to servers. To increase the schedulability of aperiodic modules, the off-line scheduling algorithm implements some simple schemes to balance the load between the sites of a distributed system and, instead of rigid start times, defines scheduling windows for periodic tasks.

An Algorithm for a Single Machine Scheduling Problem with Sequence Dependent Setup Times and Scheduling Windows

Abstract An enumeration algorithm is presented for solving a scheduling problem similar to the single machine job shop problem with sequence dependent setup times. The scheduling problem differs from the job shop problem in two ways. First, its objective is to select an optimum subset of the available tasks to be performed during a fixed period of time. Secondly, each task scheduled is constrained to occur within its particular scheduling window. The algorithm is currently being used to develop typical observational timelines for a telescope that will be operated in earth orbit. Computational times associated with timeline development are presented.