Abstract

The register file of a modern superscalar processor is a critical component of the processor pipeline that can have a large impact on processor performance. Large register files provide larger windows of speculation to the processor and allow greater levels of instruction-level parallelism. However, the access time and energy consumption of these structures can grow quite large when these structures increase in size, especially considering the number of ports required. The paper proposes an architecture that moves the large register file needed to fully exploit greater levels of instruction level parallelism off the schedule to the execute path of the processor. This is accomplished by decoupling the instruction window (the amount of instruction state maintained in the reorder buffer and register file) from the scheduling window (the working set of registers required by the instruction scheduler and execution core). The state of the scheduling window is maintained by an operand file and a speculative logical register file. The operand file stores only the set of input registers to be consumed by instructions in the issue queue, and provides low-latency and energy efficient storage for the working set of registers. This design can reduce the energy dissipation by a factor of 6.5 on average over a traditional large register file, and allows the instruction window to be scaled independently of the register file structures on the schedule to execute path.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.