Loop Scheduling Research Articles

Iterative scheduling algorithms based on the subdivision of the solution space into domains

Iterative multiprocessor scheduling algorithms are considered. The iterative algorithms make it possible to solve scheduling problems for a wide class of computer architectures but are very intricate from the computational point of view. To simplify the iterative algorithms, we propose an approach to their construction based on the subdivision of the space of correct schedules into disjoint domains, namely, an algorithm for constructing domains is proposed, the operations of the schedule transformations closed within the domains are introduced, and a technique for cutting off domains is developed. The approach developed also makes it possible to construct parallel algorithms with a low traffic of the exchange between parallel processes.

Optimized address assignment with array and loop transformations for minimizing schedule length

Reducing address arithmetic operations by optimization of address offset assignment greatly improves the performance of digital signal processor (DSP) applications. However, minimizing address operations alone may not directly reduce code size and schedule length for DSPs with multiple functional units. Little research work has been conducted on loop optimization with address offset assignment problem for architectures with multiple functional units. In this paper, we combine loop scheduling, array interleaving, and address assignment to minimize the schedule length and the number of address operations for loops on DSP architectures with multiple functional units. Array interleaving is applied to optimize address assignment for arrays in loop scheduling process. An algorithm, address operation reduction rotation scheduling (AORRS), is proposed. The algorithm minimizes both schedule length and the number of address operations. with to list scheduling, AORRS shows an average reduction of 38.4% in schedule length and an average reduction of 31.7% in the number of address operations. Compared with rotation scheduling, AORRS shows an average reduction of 15.9% in schedule length and 33.6% in the number of address operations.

Optimize Address Assignment With Array and Loop Transformations for Minimizing Schedule Length

Reducing address arithmetic operations by optimization of address offset assignment greatly improves the performance of digital signal processor (DSP) applications. However, minimizing address operations alone may not directly reduce code size and schedule length for DSPs with multiple functional units. Little research work has been conducted on loop optimization with address offset assignment problem for architectures with multiple functional units. In this paper, we combine loop scheduling, array interleaving, and address assignment to minimize the schedule length and the number of address operations for loops on DSP architectures with multiple functional units. Array interleaving is applied to optimize address assignment for arrays in loop scheduling process. An algorithm, address operation reduction rotation scheduling (AORRS), is proposed. The algorithm minimizes both schedule length and the number of address operations. with to list scheduling, AORRS shows an average reduction of 38.4% in schedule length and an average reduction of 31.7% in the number of address operations. Compared with rotation scheduling, AORRS shows an average reduction of 15.9% in schedule length and 33.6% in the number of address operations.

Iterative hybrid graph and interference aware scheduling algorithm for STDMA networks

An algorithm that combines graph colouring with signal-to-interference plus noise ratio information to allocate transmission rights in a spatial time division multiple access (STDMA) network is presented. The proposed iterative algorithm extends graph-based algorithms by allowing feasible schedules to be found with high spatial timeslot reuse.

Finding minimum flow time cyclic schedules for non-identical, multistage jobs

Finding a minimum flow time cyclic schedule for a single, multistage job with a serial, re-entrant routing is known to be NP-hard. This paper addresses the problem of scheduling multiple, non-identical jobs in a cyclic fashion, where the job routings may be arbitrary partial orders as well as re-entrant. Given a fixed cycle length, our goal is to minimize a weighted sum of the job flow times. We present a general schedule construction algorithm for implementing a cyclic version of priority dispatch rules that accepts any user-defined tie-breaking function and naturally yields a feasible cyclic schedule. We also describe a pair of easily solvable subproblems that may be used to tighten existing cyclic schedules, as well as an iterative schedule improvement algorithm based on a technique called compression. A numerical study suggests that our schedule construction algorithm, called Cyclic PDR, outperforms its traditional noncyclic priority dispatch rule counterpart, as well as a previously proposed single-pass algorithm. The Cyclic PDR algorithm is shown to be particularly effective when used in conjunction with a least work remaining tie-breaking function. Taken together, our schedule construction and improvement techniques provide an effective solution approach for producing minimum flow time cyclic schedules.

C ronus: A platform for parallel code generation based on computational geometry methods

This paper describes C ronus, a platform for parallelizing general nested loops. General nested loops contain complex loop bodies (assignments, conditionals, repetitions) and exhibit uniform loop-carried dependencies. The novelty of C ronus is twofold: (1) it determines the optimal scheduling hyperplane using the QuickHull algorithm, which is more efficient than previously used methods, and (2) it implements a simple and efficient dynamic rule (successive dynamic scheduling) for the runtime scheduling of the loop iterations along the optimal hyperplane. This scheduling policy enhances data locality and improves the makespan. C ronus provides an efficient runtime library, specifically designed for communication minimization, that performs better than more generic systems, such as Berkeley UPC. Its performance was evaluated through extensive testing. Three representative case studies are examined: the Floyd–Steinberg dithering algorithm, the Transitive Closure algorithm, and the FSBM motion estimation algorithm. The experimental results corroborate the efficiency of the parallel code. The tests show speedup ranging from 1.18 (out of the ideal 4) to 12.29 (out of the ideal 16) on distributed-systems and 3.60 (out of 4) to 15.79 (out of 16) on shared-memory systems. C ronus outperforms UPC by 5–95% depending on the test case.

On Periodic Register Need in Software Pipelining

This paper presents several theoretical and fundamental results on the register need in periodic schedules, also known as MAXLIVE. Our first contribution is a novel formula for computing the exact number of registers needed by a scheduled loop. This formula has two advantages: Its computation can be done by using a polynomial algorithm with O(n lg n) complexity (n is the number of instructions in the loop) and it allows the generalization of a previous result [13]. Second, during software pipelining, we show that the minimal number of registers needed may increase when incrementing the initiation interval (II), which is contrary to intuition. For the case of zero architectural delays in accessing registers, we provide a sufficient condition for keeping the minimal number of registers from increasing when incrementing the II. Third, we prove an interesting property that enables us to optimally compute the minimal periodic register sufficiency of a loop for all its valid periodic schedules, irrespective of II. Fourth and last, we prove that the problem of optimal stage scheduling under register constraints is polynomially solvable for a subclass of data dependence graphs, whereas this problem is known to be NP-complete for arbitrary dependence graphs [7]. Our latter result generalizes a previous achievement [13] which addressed data dependence trees and forest of trees. In this study, we consider cyclic data dependence graphs without taking into account any resource constraints. The aim of our theoretical results on the periodic register need is to help current and future software pipeliners achieve significant performance improvements by making better (if not the best) use of the available resources.

Dynamic load balancing with adaptive factoring methods in scientific applications

To improve the performance of scientific applications with parallel loops, dynamic loop scheduling methods have been proposed. Such methods address performance degradations due to load imbalance caused by predictable phenomena like nonuniform data distribution or algorithmic variance, and unpredictable phenomena such as data access latency or operating system interference. In particular, methods such as factoring, weighted factoring, adaptive weighted factoring, and adaptive factoring have been developed based on a probabilistic analysis of parallel loop iterates with variable running times. These methods have been successfully implemented in a number of applications such as: N-Body and Monte Carlo simulations, computational fluid dynamics, and radar signal processing. The focus of this paper is on adaptive weighted factoring (AWF), a method that was designed for scheduling parallel loops in time-stepping scientific applications. The main contribution of the paper is to relax the time-stepping requirement, a modification that allows the AWF to be used in any application with a parallel loop. The modification further allows the AWF to adapt to load imbalance that may occur during loop execution. Results of experiments to compare the performance of the modified AWF with the performance of the other loop scheduling methods in the context of three nontrivial applications reveal that the performance of the modified method is comparable to, and in some cases, superior to the performance of the most recently introduced adaptive factoring method.

Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation

In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression

Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems

In this brief, we propose a novel real-time loop-scheduling technique to minimize energy consumption via dynamic voltage scaling (DVS) for applications with loops considering transition overhead. One algorithm, dynamic voltage loop scheduling (DVLS), is designed integrating with DVS. In DVLS, we repeatedly regroup a loop based on rotation scheduling and decrease the energy by DVS as much as possible within a timing constraint. We conduct the experiments on a set of digital signal processing benchmarks. The experimental results show that DVLS achieves big energy saving compared with the traditional time-performance-oriented scheduling algorithm

A performance-based parallel loop scheduling on grid environments

The effectiveness of loop self-scheduling schemes has been shown on traditional multiprocessors in the past and computing clusters in the recent years. However, parallel loop scheduling has not been widely applied to computing grids, which are characterized by heterogeneous resources and dynamic environments. In this paper, a performance-based approach, taking the two characteristics above into consideration, is proposed to schedule parallel loop iterations on grid environments. Furthermore, we use a parameter, SWR, to estimate the proportion of the workload which can be scheduled statically, thus alleviating the effect of irregular workloads. Experimental results on a grid testbed show that the proposed approach can reduce the completion time for applications with regular or irregular workloads. Consequently, we claim that parallel loop scheduling can benefit applications on grid environments.

Response rate and sensitivity to the molar feedback function relating response and reinforcement rate on VI+ schedules of reinforcement.

In 5 experiments, the author examined rats' sensitivity to the molar feedback function relating response rate to reinforcement rate on schedules of reinforcement. These studies demonstrated that, at lower rates of responding, rats' performance on variable ratio (VR), variable interval (VI), and variable interval with linear feedback loop (VI+) schedules was determined largely by reinforcement of interresponse times; response rates were faster on VR than on both VI and VI+ schedules. In contrast, when procedures were adopted to maintain high rates of response, rats showed sensitivity to the molar characteristics of the schedules; they responded as fast on a VI+ schedule as on a VR schedule and faster on both of these schedules than on a yoked VI schedule. When the variance of response rate was manipulated, this factor was noted as an important element in determining sensitivity to the molar characteristics of the schedule.

Utility-based QoS optimisation strategy for multi-criteria scheduling on the grid

The paper presents quality of service (QoS) optimisation strategy for multi-criteria scheduling on the grid, based on a mathematical QoS model and a distributed iterative algorithm. Three QoS criteria are considered, namely payment, deadline and reliability, which are formulated as utility function. The optimisation problem is split into two parts: task optimisation performed on behalf of the user and resource optimisation performed on behalf of the grid. The strategy employs three types of agents: task agents responsible for task optimisation, computation resource and network resource agents responsible for resource optimisation. The agents apply economic models for optimisation purposes. Dynamic programming is used to optimise the total system utility function in terms of an iterative algorithm. The objective of multi-criteria scheduling is to maximise the global utility of the system. This paper proposes an iterative scheduling algorithm that is used to perform QoS optimisation-based multi-criteria scheduling. The proposed QoS optimisation-based multi-criteria scheduling problem solution has been practically examined by simulation experiments.

OpenMP extension to SMP clusters

This article discusses the approaches to apply the OpenMP programming model to symmetric multiprocessor (SMP) clusters using software distributed shared memory (SDSM). The major focus of this article is on the challenges that the prior studies faced and on their solution techniques. Exploiting message-passing primitives explicitly for the openMP synchronization and work-sharing directives enables light interprocess synchronizations. The studies on loop scheduling for SMP clusters will promise significant improvement in system performance. Finally, OpenMP is considered as promising programming model

A Convergence Study of the Discrete FGDLS Algorithm

The Feedback-Guided Dynamic Loop Scheduling (FGDLS) algorithm [1] is a recent dynamic approach to the scheduling of a parallel loop within a sequential outer loop. Earlier papers have analysed convergence under the assumption that the workload is a positive, continuous, function of a continuous argument (the iteration number). However, this assumption is unrealistic since it is known that the iteration number is a discrete variable. In this paper we extend the proof of convergence of the algorithm to the case where the iteration number is treated as a discrete variable. We are able to establish convergence of the FGDLS algorithm for the case when the workload is monotonically decreasing.

Loop scheduling with timing and switching-activity minimization for VLIW DSP

In embedded systems, high-performance DSP needs to be performed not only with high-data throughput but also with low-power consumption. This article develops an instruction-level loop-scheduling technique to reduce both execution time and bus-switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can reduce both schedule length and bus-switching activities. Compared with the work of Lee et al. [2003], SAMLS shows an average 11.5% reduction in schedule length and an average 19.4% reduction in bus-switching activities.

Applying the Feedback Guided Dynamic Loop Scheduling Method for the Shortest Path Problem

Feedback Guided Dynamic Loop Scheduling is a recent dynamic method for loop scheduling. The method has been mainly studied for synthetic examples so far and it has always offered the lowest computational times against other dynamic scheduling methods. In this article we show how the method is applied to the shortest path problem and also present some execution times that prove the efficiency.

PARALLEL ADAPTIVE QUANTUM TRAJECTORY METHOD FOR WAVEPACKET SIMULATIONS

Time-dependent wavepackets are widely used to model various phenomena in physics. One approach in simulating the wavepacket dynamics is the quantum trajectory method (QTM). Based on the hydrodynamic formulation of quantum mechanics, the QTM represents the wavepacket by an unstructured set of pseudoparticles whose trajectories are coupled by the quantum potential. The governing equations for the pseudoparticle trajectories are solved using a computationally-intensive moving weighted least squares (MWLS) algorithm, and the trajectories can be computed in parallel. This paper contributes a strategy for improving the performance of wavepacket simulations using the QTM. Specifically, adaptivity is incorporated into the MWLS algorithm, and loop scheduling techniques are employed to dynamically load balance the parallel computation of the trajectories. The adaptive MWLS algorithm reduces the amount of computations without sacrificing accuracy, while adaptive loop scheduling addresses the load imbalance introduced by the algorithm and the runtime system. Results of experiments on a Linux cluster are presented to confirm that the adaptive MWLS reduces the trajectory computation time by up to 24%, and adaptive loop scheduling achieves parallel efficiencies of up to 85% when simulating a free particle.

An Enhanced Parallel Loop Self-Scheduling Scheme for Cluster Environments

Approaches for dealing with scheduling and load-balancing in PC-based cluster systems are famous and well known. In such environments, Self-Scheduling Schemes are suitable for parallel loops with independent iterations. However, while schemes such as FSS, GSS, and TSS fit most computer systems, they cannot provide good load-balancing. Chao-Tung Yang and Shun-Chi Chang proposed a parallel loop scheduling scheme for heterogeneous PC cluster systems in Yang and Chang [13]. Though the proposed scheme allows users to choose parameters before execution initialization, weaknesses in it motivated us to develop further improvements. For instance, using fixed and monotonous parameters can easily lead to invalid scheduling due to use of previously input information. Thus, in this paper we propose a new scheme that fits most widely available computer systems and allows the scheduling parameter to be adjusted dynamically in order to provide higher overall performance.

Design and analysis of a class-aware recursive loop scheduler for class-based scheduling

In this paper, we consider the problem of devising a loop scheduler that allocates slots to users according to their relative weights as smoothly as possible. Instead of the existing notion of smoothness based on balancedness, we propose a variance-based metric which is more intuitive and easier to compute. We propose a recursive loop scheduler for a class-based scheduling scenario based on an optimal weighted round-robin scheduler. We show that it achieves very good allocation smoothness with almost no degradation in intra-class fairness. In addition, we also demonstrate the equivalence between our proposed metric and the balancedness-based metric.