Scheduling In High-level Synthesis Research Articles

Concurrent BIST Synthesis and Test Scheduling Using Genetic Algorithms

This paper presents an efficient method for concurrent built-in self-test synthesis and test scheduling in high-level synthesis. The method maximizes concurrent testing of modules while performing the allocation of functional units, test registers, and interconnects. The method is based on a genetic algorithm that efficiently explores the testable design space and finds a sub-optimal test registers assignment for each k-test session. The method was implemented using C+ + on a Linux workstation. Several benchmark examples have been implemented and favorable design comparisons are reported.

Constraints-driven scheduling and resource assignment

This paper describes a new method for modeling and solving different scheduling and resource assignment problems that are common in high-level synthesis (HLS) and system-level synthesis. It addresses assignment of resources for operations and tasks as well as their static, off-line scheduling. Different heterogeneous constraints are considered for these problems. These constraints can be grouped into two classes: problem-specific constraints and design-oriented constraints. They are uniformly modeled, in our approach, by finite domain (FD) constraints and solved using related constrained programming (CP) techniques. This provides a way to improve quality of final solutions. We have developed in Java a constraint solver engine, JaCoP ( Ja va Co nstraint P rogramming), to evaluate this approach. This solver and a related framework make it possible to model different resource assignment and scheduling problems, and handle them uniformly. The JaCoP prototype system has been extensively evaluated on a number of HLS and system-level synthesis benchmarks. We have been able to obtain optimal results together with related proofs of optimality for all HLS scheduling benchmarks and for all explored design styles (except one functional pipeline design). Many system-level benchmarks can also be solved optimally. For large randomly generated task graphs, we have used heuristic search methods and obtained results that are 1--3% worse than lower bounds or optimal results. These experiments have proved the feasibility of the presented approach.

Lower bound estimation of hardware resources for scheduling in high-level synthesis

In high-level synthesis of VLSI circuits, good lower bound prediction can efficiently narrow down the large space of possible designs. Previous approaches predict the lower bound by relaxing or even ignoring the precedence constraints of the data flow graph (DFG), and result in inaccuracy of the lower bound. The loop folding and conditional branch were also not considered. In this paper, a new stepwise refinement algorithm is proposed, which takes consideration of precedence constraints of the DFG to estimate the lower bound of hardware resources under time constraints. Processing techniques to handle multi-cycle. chaining, pipelining, as well as loop folding and mutual exclusion among conditional branches are also incorporated in the algorithm. Experimental results show that the algorithm can produce a very tight and close to optimal lower bound in reasonable computation time.

Maximum weighted independent sets on transitive graphs and applications

We present a polynomial-time algorithm that finds the maximum weighted independent set of a transitive graph. The studied problem finds applications in a variety of VLSI contexts, including path delay fault testing, scheduling in high-level synthesis, and channel routing in physical design automation. The algorithm has been implemented and incorporated in a CAD tool for path delay fault testing. We experimentally verify its impact in the latter context.

Net scheduling in high-level synthesis

A new net scheduling and allocation model generates net schedules that minimize either execution time or resources. The author tested the model within a VHDL-based high-level synthesis system called Ahiles.

Complexity of Scheduling in High Level Synthesis

This work examines the complexity of scheduling for high level synthesis. It has been shown that the problem of finding the minimum time schedule for a set of chains of operations of two types using two processors, one of each type, is NP‐complete. However, for two chains only, a polynomial time algorithm can been obtained for scheduling with two processors. The problem of scheduling a rooted binary tree of two operation types on two processors, one of each type, has been shown to be NP‐complete. It has also been proved that absolute approximations for schedule length minimization or processor minimization are NP‐complete. A related resource constrained scheduling problem has also been shown to be NP‐hard.

SALSA: a new approach to scheduling with timing constraints

An approach to scheduling in high-level synthesis that meets timing constraints while attempting to minimize hardware resource costs is described. The approach is based on a modified control/data-flow graph (CDFG) representation called SALSA. SALSA provides a simple move set that allows alternative schedules to be quickly explored while maintaining timing constraints. It is shown that this move set is complete in that any legal schedule can be reached using some sequence of move applications. In addition, SALSA provides support for scheduling with conditionals, loops, and subroutines. Scheduling with SALSA is performed in two steps. First, an initial schedule that meets timing constraints is generated using a constraint solution algorithm adapted from layout compaction. Second, the schedule is improved using the SALSA move set under control of a simulated annealing algorithm. Results show the scheduler's ability to find good schedules which meet timing constraints in reasonable execution times.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>