Scanning Electron Beam Lithography Research Articles

Carbon Nanotube Based Magnetic Tunnel Junctions for Electromagnetic Nondestructive Evaluation

AbstractSpin coherent transport in carbon nanotubes enables single-nanotube devices for magnetic field sensing. This unique transport property of single walled carbon nanotubes (SWCNTs) has been studied for development into advanced sensors for nondestructive evaluation (NDE). Coupling of a single walled carbon nanotube to ferromagnetic electrodes is predicted to form a carbon nanotube magnetic tunnel junction. Fabrication of such devices has been performed through scanning probe and electron beam lithography. Purified single walled carbon nanotubes are deposited across electrodes to complete device fabrication. A spincoherent quantum transport theory based on a nonequilibrium Green's function method has been established to predict conductance and magnetoconductance across junctions. Experimental measurements of the room temperature conductance of Cobalt/SWCNT/Cobalt junctions have been performed.

DY-7 sub-0.1 micron EB lithography system

A scanning electron beam lithography system with a field size of 1×1 mm has been built for the delineation of sub-0.1 μm patterns. The system comprises a 30-kV LaB6 electron gun with a zoom lens arrangement of a condenser doublet. To minimize the aberrations, a combined magnetic focusing and deflection system with prelens double deflection is adopted and optimized. To avoid the often-appearing problem with multi-variable optimization process, i.e. the ultimate results depend on the initial values, a practical way is suggested. Instead of the conventional coil-winding deflector, a saddle coil deflector consisted of electrodes fabricated by wire electron discharge machining (WEDM) is employed to gain higher geometrical accuracy and lower inductance. To increase writing speed and accuracy, we have developed a multi-function pattern generator to perform the writing of trapezoids, polygons, circles, rings as well as rectangles directly through hardware. In addition, a novel approach for linear and non-linear correction of patterns is introduced to improve the scan accuracy. The system has been used to delineate nanometer-scale patterns in both PMMA and ZEP 520 electronic resists on thick Si substrates over a field size of 1×1 mm. A lithographic example with the system is shown.

Nanofabrication by direct epitaxial growth

We describe a novel, all dry approach that uses direct epitaxial growth for nanostructure fabrication. The two major requirements for achieving direct epitaxial growth are the ability to generate and to subsequently maintain and control spatial and chemical selectivity in the film growth process. The spatial selectivity is generated by pattering a surface adsorption layer on Si(100) using scanning electron beam lithography. This artificial lateral variation in surface reactivity is used as a template in subsequent epitaxy. Selective epitaxial growth on the resulting patterns is achieved by supersonic molecular jet epitaxy. Systematic investigation of the effects of various patterning and growth parameters on spatial and chemical selectivity at a sub- 100-nm feature scale using hydrogen terminated and nitrogen terminated growing Si(100) surfaces are presented.

Deep ultraviolet resists AZ DX-561 and AZ DX-1300P applied for electron beam and masked ion beam lithography

This article reports work on two positive-tone deep ultraviolet chemically amplified resist (CAR) systems from HOECHST AG that were applied in two different lithographic processes: (i) the AZ DX-561 resist in serial working direct-write scanning electron-beam lithography, and (ii) AZ DX-1300P resist in a novel parallel working masked ion beam lithography. The main parameters of both CARs under the optimized processing conditions for both lithographic processes were generally determined. The contrast of these resists was found to be >10. The sensitivity of AZ DX-561 was about 12 μC/cm2 for 30 keV electrons. For AZ DX-1300P, a sensitivity of 9 μC/cm2 was found for 30 keV electrons and 0.3 μC/cm2 for 80 keV He+ ions. Both resists showed excellent performance for subsequent reactive ion etching.

Analogue delay-locked loop for spatial-phase locking

An analogue delay-locked loop has been developed for spatial-phase locking in a scanning electron-beam lithography system. The loop improves pattern-placement precision to 3σ ≃ 12 nm, by referencing all writing to a 400 nm-period grating. Results compare well with a numerical simulation.

Fabrication of Aharonov-Bohm rings in Si/SiGe heterostructure

A sub-micron trenching technique has been developed to fabricate Aharonov-Bohm ring structures in a high mobility Si/Si 0.7Ge 0.3 modulation doped heterostructure. Scanning electron-beam lithography is used to expose the area defining the ring contour, and reactive-ion etching follows to recess this area, thus forcing electrons to flow inside the ring. Conductance in the Si/SiGe rings exhibits oscillations in magnetoresistance, which is the first observation of this effect in Si-based materials. The amplitude of the oscillations is comparable to that of similar devices on similar mobility GaAs/GaAlAs heterostructures.

Optimum switching time for a beam-size switch (250 nm ⇔ 1000 nm) in a vector scan electron beam lithography machine

Abstract In a vector scan electron beam lithography machine with a beam-size switch the small spot is used to write a feature sleeve for good edge acuity, while the large spot is used for fast feature fill-in. Features are broken down into writable ‘shapes’. Switching can be done once per shape, sub-field, main-field or plate. Which strategy is optimal depends on numerous system properties. For this project a 10 ms main-field switch resulted. Various implementations have been investigated for beam-size switches with switching times from 10 ns to 1 s.

Challenges in Lithographic Materials and Processes

In the last decade, major advances in fabricating VLSI electronic devices have placed increasing demands on microlithography, the technology used to generate today's integrated circuits. In 1976, state-of-the-art devices contained several thousand transistors with minimum features of 5 to 6 μm. Today, they have several million transistors and minimum features of less than 0.7 μm. Within the next 10 to 15 years, a new form of lithography will be required that routinely produces features of less than 0.25 μm. Short-wavelength (deep-UV) photolithography and scanning electron-beam, X-ray, and scanning ion-beam lithography are the possible alternatives to conventional photolithography. However, each needs new resists and processes. When deep-UV photolithography is implemented, it will represent the first widespread use in manufacture of a lithographic technology that requires an entirely new resist technology. We describe the development of a resist system that meets all requirements of the deep-UV technique.

Definition of geometries with complicated, curved boundaries for electron beam pattern generation

To facilitate the design of complicated, curved structures, we have added some new tools to a commercial IC layout system. These tools are used to approximate such structures by a large number of abutting polygons with up to 200 vertices each. Vector scan electron beam lithography systems are well suited for pattern generation of these structures, and we have created a lot of complicated structures this way.

Fabrication of fully scaled 0.5-μm n-type metal–oxide semiconductor test devices using synchrotron x-ray lithography: Overlay, resist processes, and device fabrication

Functional, fully scaled n-type metal–oxide semiconductor (NMOS) circuits with 0.5-μm ground rules have been fabricated using synchrotron radiation x-ray lithography for all device levels. The exposures were done at the vacuum ultraviolet storage ring of the National Synchrotron Light Source at Brookhaven National Laboratory using a mask/wafer aligner developed at IBM Research. The system is capable of step-and-repeat exposures covering 125-mm wafers. The mask and wafer are held in a near-vertical plane and a scanning dark-field alignment technique is used to register mask to wafer with a proximity gap of 40 μm. A scanning mirror in the beamline sweeps the x-ray beam up and down over the exposure area to achieve uniform exposure over the 25×25 mm2 exposure field used for this experiment. Exposures were done in 20 Torr of helium to provide cooling for the mask. Both positive and negative tone single-layer resists were used. The mask set consists of four light-field masks patterned on silicon substrates with electroplated gold absorbers; patterns were written by a vector scan electron beam lithography system. The performance of the aligner on both test wafers and device wafers is discussed, with emphasis on overlay and linewidth control. The repeatability of the alignment and the overall level-to-level overlay are described. Characteristics of the fabricated devices are also presented.

Electron-beam programming and testing of complementary metal-oxide semiconductor systems

This paper describes the application of a scanning electron beam lithography system (SEBL) to the programming and testing of digital CMOS systems via the direct injection of charge into the integrated circuits. E‐beam programmable interconnect structures, using floating‐gate FETs, implement customization and fault avoidance techniques. E‐beam controlled stimulus/response testing circuits, using substrate diodes, provide access to internal circuit nodes and thereby permit efficient testing procedures for large systems. Two system‐level applications are presented—a digital multiplier and a crosspoint switch. In both cases, redundant circuit components and programmable interconnect are used to achieve fault tolerance and yield enhancement. An analysis of a wafer‐scale crosspoint switch design indicates that e‐beam restructuring techniques could be used to implement an 80×75 element array on a 4‐in. wafer with 99% yield. The e‐beam programming and testing circuits are shown to be compatible with commercial CMOS foundry services. The precision, speed, and automation of the SEBL system make these techniques practical for large‐scale digital systems.

A review of submicron lithography

The techniques of submicron lithography are reviewed with special attention to the sub-100 nm region and the needs of university research. We show that high contrast resists or contrast-enhancement schemes are crucial if one is to extend the useful range of lithographic techniques to near their resolution limits. Resist sensitivity must be properly chosen in order to avoid line-edge uncertainty due to shot noise. Optical projection lithography is readily extended into the deep submicron region, in part because of the statistical advantage of low energy photons. Holographic lithography is the preferred technique for periodic and quasi-periodic patterns, at least down to 0.1 μm linewidths. The high capital and operating costs of scanning-electron-beam lithography (SEBL), are significant impediments to expanded research on applications of artificial microstructures in the submicron and sub-100 nm regions. Replication techniques, such as soft-contact photolithography, x-ray lithography and masked-ion-beam lithography do not have the flexibility of SEBL but they have good throughput and are low cost, convenient and effective. These replication techniques could greatly facilitate sub-100 nm research if methods of gap control and sub-30 nm alignment were available.

EBS-5: A vector scan electron-beam lithography system for research applications

EBS-5 is a vector scan electron beam lithography system for research and development which evolved from the EBS-4 system developed by Hughes Research Laboratories in 1977–1980. The EBS-5 system features higher throughput, improved diagnostics, and more user friendly software. The computer architecture of EBS-5 consists of a Micro VAX computer and a distributed microprocessor control system, which achieves continuous writing speeds of 13 MHz. A deflection amplifier has been developed which achieves a rise time of 80 ns. The ratio of noise and drift currents to the signal current is lower than 1×10−5 in both the deflection amplifier and the lens supplies to ensure the reproducible exposure of submicron patterns. Extensive software was developed to support the layout and fracturing of pattern data.

Scanning electron beam lithography

This paper discusses the role of scanning electron beam lithography in semiconductor microcircuit production and in the experimental fabrication of devices in the laboratory. It also describes the electron optical equipment developed for these applications.Electron beam lithography has found an important place in integrated circuit production through its ability to produce structures without masks, rather than because it can produce high resolution. Resolution, however, has been important in research and development where electron beams have been used to produce smaller devices than any other method. Many early micron and sub-micron large scale integration devices were built first with electron beams, and structures as small as a few tens of nanometers have been made for electrical characterization.Optical methods are generally more economical than electron beams for the routine production of microcircuits because exposure rates are higher and system costs are lower. Resolution with optical lithography is adequate for all devices likely to be in production in the next few years (minimum linewidth 0.75μ - 2μ) so electron beams at present only offer an advantage in fabricating masks, or in exposing customized wafers where masks are not replicated a sufficiently large number of times to offset their cost.

Proximity effect correction for electron beam lithography by equalization of background dose

Compensation for the proximity effect in electron lithography can be achieved by equalization of the backscattered dose received by all pattern points. This is accomplished by exposing the reverse tone of the required pattern with a beam diameter dc=2σb ×(1+ηe)−1/4 and dose Qc=Qe ×[ηe/(1+ηe)], where σb is the radius of the Gaussian spatial distribution function of backscattered electrons at normally exposed pixels, ηe is the ratio of backscattered to forwardscattered energy, and Qe is the dose delivered to normally exposed pixels. This correction method has been confirmed to work for 500-nm features by computer simulation of electron beam exposure and development and by experiment on a raster scan electron beam lithography system.

An overview of pattern data preparation for vector scan electron beam lithography

An overview is given of a pattern data preparation system which changes computer-aided design (CAD) data to data which drives the pattern generator of a vector scan electron beam system. The software described is basically independent of the particular CAD system or electron beam system, and is joined to these two systems by custom formatting modules. Internally, the pattern data preparation system performs a series of functions on the original design data, with the functions falling into two general classes — those which operate on individual shapes (such as etching), and those which depend on shape–shape interrelationships (e.g. dose correction, overlap removal, etc.). The design data may be described in a compacted ’’nested’’ form, or in an extended ’’unnested’’ form. Shape interrelationship manipulations cannot be simply applied to nested data, which implies that CPU time efficiency may suffer if certain operations are performed. Within this framework we describe the importance of performing manipulations in a particular order, methods for removing overlaps and for shape breakup prior to dose correction, and sorting techniques for optimizing electron beam writing performance. We also discuss methods for renesting data which has previously been unnested, and for dealing with memory arrays. The overall structure of such a software package is shown to permit system independence, and also to permit the path from CAD system to electron beam system to include only those functions which are appropriate to the device technology to which the vector scan system is applied.

X-ray lithography — A review and assessment of future applications

The radiation used in x-ray lithography spans a rather broad range, from about 4 to 50 Å. At the short wavelength end, transmission through mask membranes and vacuum windows is high, and minimum linewidth is of the order of 1/2 μm. At the long wavelength end, mask selection is limited, exposure is done in vacuum and minimum linewidth is about 100 Å. At intermediate wavelengths, one can make numerous tradeoffs among resolution, system configuration, masks and resists. X-ray lithography at the AlK wavelength (8.34 Å) is compared with scanning electron beam lithography from the point of view of exposure time, assuming a step-and-repeat strategy. The use of gap adjustment to compensate for homogeneous substrate distortion may be an important advantage of x-ray lithography relative to other parallel exposure techniques.

X-ray zone plates fabricated using electron-beam and x-ray lithography

Fresnel zone plate patterns, free of spherical aberration, with diameters of up to 0.63 mm and linewidths as small as 1000 Å were fabricated on polyimide membrane x-ray masks using scanning electron beam lithography. Distortion of the electron beam scan raster was reduced to ?2500 Å over a 2×2 mm field by applying deflection corrections, while viewing the distortion using a Moiré method. CK x-ray lithography was used to replicate the zone plate pattern in thick PMMA over a 100 Å thick plating base on a glass substrate. Zones plates in 1.3 μm thick gold were fabricated by plating, and made free-standing by removal of the plating base and the supporting glass substrate. Zone plates were tested as imaging elements with visible light and soft x-rays.

1 µm MOSFET VLSI technology: Part VIII—Radiation effects

In this paper the effect of electron-beam radiation on polysilicon-gate MOSFET's is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used. It is shown that in addition to the threshold voltage shift, caused by the accumulation of radiation-induced positive charge in the gate oxides, these charged centers and additional uncharged (neutral) electron traps lead to an increase in the electron trapping in irradiated oxides. Temperatures above 550°C are shown to be required to anneal both the positive and neutral traps completely from the oxide underlying polysilicon after exposure to radiation. Annealing of the radiation-induced positive charge from the oxide is shown to depend on the metallurgy overlying the gate insulator during heat treatment. Annealing treatments which remove the charged centers from aluminum-gated MOS structures are demonstrated to leave small (about 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ) but significant amounts of charge in certain polysilicon-gate structures. The dependence of positive and neutral trap densities on direct electron-beam exposure was studied in the range between 10 and 200 µC/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Studies on the electron-beam fabricated devices indicate that indirect exposure of the gate oxide by electrons scattered from the primary beam during lithography in areas away from the gate oxide is sufficient to cause appreciable damage. After postmetal annealing at 400° C for 20 min, the minimum residual charge density found in the electron-beam fabricated devices is 4 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> .

1 µm MOSFET VLSI technology: Part VI—Electron-beam lithography

This paper discusses the fabrication of 1 µm minimum linewidth FET polysilicon-gate devices and circuits. These were designed for the tight dimensional ground rules (resolution, linewidth control, and overlay) achievable using direct wafer write scanning electron-beam lithography with individual chip registration. The present work focuses on vector-scan electron-beam technology and processing, while other papers in this series discuss other aspects of the work. Different types of 1 µm MOSFET chips were written on 57 mm Si wafers using a totally automated electron-beam system which performs table stepping, registration to fiducial marks, and pattern writing in a vector scan mode (on an individual shape basis) with control of exposure dose for individual shapes. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance between shapes. A novel two-layer positive resist system has been developed to achieve reproducible liftoff profiles over topography and better linewidth control. The final results presented here demonstrate that there are no fundamental barriers to the extension of this work to small dimensions.