VLSI Technology Scales Research Articles

Electrostatic performance improvement of dual material cylindrical gate MOSFET using work-function modulation technique

In a continuous effort to increase the DC and RF figure-of-merits (FOMs), multigate MOSFETs have evolved from classical planar device into a gate all around structure. The unique design with accuracy in device performance has made it a cutting edge device to overcome the scaling and performance barrier of the present VLSI technology. The fabrication process of a surface channel device with proper threshold voltage (Vth) directly depends upon the work-function of the gate electrode. By keeping it in mind, a metal gate with linearly modulated work-function (5–4.2 ev) along the z-axis in a cylindrical surrounding gate MOSFET is introduced. This work demonstrates the potential benefits of work-function modulation based dual material cylindrical gate MOSFET (WMDMCG) in terms of DC performance characteristics. The present model provides improved DC performance as compared to conventional dual material cylindrical surrounding gate MOSFET (DMCG) and the results obtained are validated with TCAD device simulator from Synopsys.

Scalable Bang–Bang Phase-Locked-Loop-based integrated sensor interfaces

The scaling of VLSI technology results in reduced supply voltages, hence jeopardizing the voltage swing and signal-to-noise ratio achievable by analog integrated circuits. An alternative is to take advantage of the increased timing resolution of faster CMOS technologies, and to replace traditional voltage-mode processing by time-based circuits. Time-based design enables us to implement highly-digital sensor interfaces, which can benefit from scaling in terms of area reduction, compared to analog implementations. In addition, it enables low-voltage and low-power design. This invited overview paper gives a survey of one type of such time-based sensor interfaces: the Bang–Bang Phase-Locked-Loop-based Sensor-to-Digital Converter. The highly-digital implementation of the frequency-based sensor interface results in low-voltage, low-power, robust and highly-scalable designs. Several design examples are elaborated, each focusing on a different design aspect.

A Combined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices to Low Voltage Fault Attacks

The continuous scaling of VLSI technology and the possibility to run circuits in subthreshold voltage range make it possible to implement standard cryptographic primitives within the very limited circuit and power budget of radio frequency identification (RFID) devices. However, such cryptographic implementations raise concerns regarding their vulnerability to both active and passive side-channel attacks. In particular, when focusing on RFID targeted designs, it is important to evaluate their resistance against low-cost physical attacks. A low-cost fault injection attack can be mounted, for example, by lowering the supply voltage of the chip with the goal of causing setup time violations. In this paper, we provide an in-depth characterization of a chip implementation of the AES cipher. The chip has been designed using a 65-nm low-power standard cell library and operates in a subthreshold voltage range. We first show that it is possible to inject faults (through lowering the supply voltage) compliant with the fault models required to perform attacks against the AES cipher. We then investigate the possibility of predicting, at design time, which parts of the chip are more likely to be sensitive to such fault injection attacks and produce the desirable (from the point of view of the attacker) faulty behavior. Identifying such sensitive logic signals allows us to suggest to the designer a tailored countermeasure strategy for thwarting these attacks, with a minimal impact on the circuit's performance.

Arsenic Dimer (As2 +) Lightly Doped Drain (LDD) Implantation Study for 20nm Logic Device Development

Process variation presents a significant challenge to future scaling of VLSI technology. Junction depth scaling with small Vth variation is required for the 45 nm technology node and beyond. Variations in MOSFET characteristics due to random dopant fluctuation (RDF) may become a fundamental limit to device scaling and circuit complexity. Arsenic dimer (As2 +) implant has been used for the formation of ultra-shallow source drain extensions for NMOS transistors below 45nm, CMOS logic process. As Dimer requires only half the dose and twice the energy of equivalent As+ so it is more favorable for much lower energy (＜ƒ5KeV) implantation. A comparison of electrical parameters including drive current, Rtotal, junction breakdown voltage, gate to drain overlap capacitance and dopant SMIS profile indicates equivalent process performance for dimer and As+ implantation. However, arsenic dimer implantation showed better Vth mismatch performance than conventional As+ implantation.

Fault Reduction in Nonoscale VLSI Interconnection by Using Carbon Nanotubes Technology

As the VLSI technology scales down, significant challenges are facing the fabrication, modeling, and performance of the integrated circuits. One of the major challenges for the continuiation of the Moore’s law is “interconnects” at nano-scale. Interconnects become as important as transistors in the current technologies and will dominate the chip performance at the future technologies. Beside their eletrical performance, their mechanical performnace will be important at the nano-scale. Wires should be resilient enough to cope with Back-End-Of-Line (BEOL) processes. Nano-technology has offered us many solutions to current technology problems. One of the major gift of this technology is Carbon Nanotubes (CNT). CNTs are a promising candidate to replace copper interconnects. They not only provide us with ballistic transport for semiconductors, but also have better mechanical performance. In this paper, we study the mechanical reliability of the CNT interconnects and compare it with their copper conterparts.

Vertical Assembly of Carbon Nanotubes for VLSI Via Interconnection

As VLSI technologies scale down, the performance of copper interconnects is greatly degraded by the electromigration problems. The alternative interconnect materials need to be developed. Carbon nanotubes (CNTs) have emerged as a promising nanostructured materials for interconnect applications in the future integrated circuits (ICs) due to their unique molecular structure and excellent properties. In this paper, we have developed a new via interconnection technique by employing alternating current dielectrophoresis (AC-DEP) of the CNT bundles at room temperature. By predefining via holes, high density CNTs have been successfully assembled using AC-DEP technique between the top and bottom electrodes. Our method is controllable, scalable and also compatible with conventional CMOS process, which demonstrates that the carbon nanotubes can be used as interconnects in future VLSI circuits.

Giga bit per second Differential Scheme for High Speed Interconnect

The performance of many digital systems today is limited by the interconnection bandwidth between chips. Although the processing performance of a single chip has increased dramatically since the inception of the integrated circuit technology, the communication bandwidth between chips has not enjoyed as much benefit. Most CMOS chips, when communicating off-chip, drive unterminated lines with full-swing CMOS drivers. Such full-swing CMOS interconnect ring-up the line, and hence has a bandwidth that is limited by the length of the line rather than the performance of the semiconductor technology. Thus, as VLSI technology scales, the pin bandwidth does not improve with the technology, but rather remains limited by board and cable geometry, making off-chip bandwidth an even more critical bottleneck. In order to increase the I/O Bandwidth, some efficient high speed signaling standard must be used which considers the line termination, signal integrity, power dissipation, noise immunity etc In this work, a transmitter has been developed for high speed offchip communication. It consists of low speed input buffer, serializer which converts parallel input data into serial data and a current mode driver which converts the voltage mode input signals into current over the transmission line. Output of 32 low speed input buffers is fed to two serializer, each serializer converting 16 bit parallel data into serial data stream. Output of two serializers is fed to LVDS current mode driver. The serial link technique used in this work is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the receiver end. Serial link is the design of choice in any application where the cost of the communication channel is high and duplicating the links in large numbers is uneconomical.

Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation

As the VLSI technologies scale down to the sub-wavelength lithographic regime, the process parameter variations lead to severe variability of chip performances. Among many process parameter variations, the gate length variation is one of the most important sources of circuit performance variation. This paper proposes a gate layout pattern regularity enhancement method to reduce the systematic variation of the gate critical dimensions (CD). The proposed method performs a decompaction of a cell layout considering the on-pitch constraints and enhances the pattern regularity under given timing constraints using linear programming. We can enhance the regularity under the timing constraint by modifying non-timing-critical patterns using the proposed method. Experimental results show that 73.7% gate layouts of 25 cells in a 90nm technology are placed perfectly on-pitch by the proposed method with 10% allowable delay increase. Experiment on the edge placement error (EPE) estimation shows that the standard deviation of the gate CD EPE distribution is reduced by about 28% compared to that of the original layouts. These results show that the proposed method is effective for reducing the systematic CD variation.

A Fast OPC Algorithm for IC Layout Based on 1-D Cells after Optimization of Gap Distribution

As VLSI technology scales down to 45nm process node, reliable printing becomes a persistent huge challenge to IC's manufacturability. The limitation of RETs now forces people to adopt a regular 1-D cell design methodology. A method of extending the line-ends and inserting dummies to optimize the gap distribution, with which the layout based on 1-D cells could get better printability, has been proposed in recent studies. In this paper, we present a fast OPC algorithm for IC layout based on 1-D cells after the previously proposed optimization of gap distribution. With this algorithm, during the OPC process, the extended parts and dummies of the layout are excluded from correction to save run time, and only the functional parts of the layout will be corrected. Experimental results on 45 nm process show excellent efficiency of this algorithm.

ASIC design flow considering lithography-induced effects

As VLSI technology scales towards 65 nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people often treat systematic components of the variations, which are generally traceable according to process models, in the same way as random variations in process corner-based methodologies. In particular, lithography-induced process variations are usually estimated by a universal worst-case value without considering their layout environment. Consequently, the process corner models based on such estimation are unnecessarily pessimistic. A new ASIC design methodology that captures lithography-induced polysilicon gate length variations including both the layout dependent systematic components and random components is proposed. This methodology also shows that lookup table methodology is sufficient to handle back end of line lithography process variations in timing analysis. In addition, a new technique of dummy poly insertion is suggested to shield inter-cell optical interferences. This technique together with standard cells characterised using the new methodology will let current design flows comprehend the variations almost without any changes. More importantly, by separating systematic lithography effect from random process variations, this methodology greatly reduces pessimism in timing analysis, thus enabling both aggressive design implementation and easier timing signoff. Experimental results on industrial designs indicate that the new methodology can averagely reduce timing variation window by 11% and power variation window by 55% when compared with a worst-case approach.

Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing

As VLSI technologies scale down, interconnect performance is greatly affected by crosstalk noise due to the decreasing wire separation and increased wire aspect ratio, and crosstalk has become a major bottleneck for design closure. The effectiveness of traditional buffering and spacing techniques for noise reduction is constrained by the limited available resources on chip. In this paper, we present a method for incorporating crosstalk reduction criteria into global routing under a broad power supply network paradigm. This method utilizes power/ground wires as shields between signal wires to reduce capacitive coupling, while considering the constraints imposed by limited routing and buffering resources. An iterative procedure is employed to route signal wires, assign supply shields, and insert buffers so that both buffer/routing capacity and signal integrity goals are met. In each iteration, shield assignment and buffer insertion are considered simultaneously via a dynamic programming-like approach. Our noise calculations are based on Devgan's metric, and our work demonstrates, for the first time, that this metric shows good fidelity on average. An effective noise margin inflation technique is also proposed to compensate for the pessimism of Devgan's metric. Experimental results on testcases with up to about 10000 nets point towards an asymptotic runtime that increases linearly with the number of nets. Our algorithm achieves noise reduction improvements of up to 53% and 28%, respectively, compared to methods considering only buffer insertion or only shield insertion after buffer planning.

POMR: a power-aware interconnect optimization methodology

As VLSI technologies scale down, the average die size is expected to remain constant or to slightly increase with each generation. This results in an average increase in the global interconnect lengths. To mitigate their impact, buffer insertion has become the most widely used technique. However, unconstrained buffering is expected to require several hundreds of thousands of global interconnect buffers. This increased number of buffers is destined to adversely impact the chip power consumption. In this paper, an optimal power maze routing and buffer insertion/sizing problem for a two-pin net is formulated, as a shortest paths ranking problem. The pseudopolynomial time bound of the new formulation fits well within the context of the increased number of buffers. In fact, power savings as high as 25% for the 130-nm technology with a 10% sacrifice in delay is achieved. Furthermore, with the advent of dual threshold technologies, power sensitive applications can substantially benefit from adopting dual threshold buffers. Accordingly, the proposed problem formulation is extended to incorporate the selection of the buffer threshold voltage, where a twofold increase in power savings is observed. During the assessment of the impact of technology scaling using a set of MCNC Benchmarks, an average power saving as high as 35% with a 10% sacrifice in delay is observed. In addition, there is a 10% variation in the power savings when accounting for the process variations.

Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

Process variations as a percentage of nominal delay and power consumption are becoming more and more severe with continuing scaling of VLSI technology. The worsening process variation causes increased variability in performance, power, and reliability of VLSI circuits. Thus, performance and power consumption targets obtained during the design phase of VLSI circuits may significantly deviate from that of actual silicon resulting in significant yield losses. Adaptive body bias (ABB) has been shown to be an effective method of postsilicon tuning to reduce variability under the presence of process variation. Post silicon tuning can also be accomplished by using adaptive supply voltage (ASV). This paper compares the effectiveness of ABB and ASV in reducing variability and improving performance and power, and thus, yield.

Smart Memories

Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general purpose designs. To address these conflicting requirements, we propose a modular reconfigurable architecture called Smart Memories, targeted at computing needs in the 0.1μ technology generation. A Smart Memories chip is made up of many processing tiles, each containing local memory, local interconnect, and a processor core. For efficient computation under a wide class of possible applications, the memories, the wires, and the computational model can all be altered to match the applications. To show the applicability of this design, two very different machines at opposite ends of the architectural spectrum, the Imagine stream processor and the Hydra speculative multiprocessor, are mapped onto the Smart Memories computing substrate. Simulations of the mappings show that the Smart Memories architecture can successfully map these architectures with only modest performance degradation.

Data converters for communication systems

Data converters are playing an ever increasingly important role in digital communication channels. As VLSI technologies scale, more of the signal processing is performed in the digital domain, making superior converter design critical. Attributes of various modern analog-to-digital converters such as flash and /spl Sigma//spl Delta/ are described.

Effect of VLSI technology scaling on ESD current-carrying capability

The ultimate defense against electrostatic discharge (ESD) damage is the robustness of individual transistors. This paper investigates the impact of VLSI scaling on this defense capability. For scaling from 1 to 0.1 μm, the current-carrying capability of MOS transistors decreases if the scaling law is strictly followed. However, if one relaxes the scaling in the device width dimension to κ 0.3, instead of κ, where κ is the scaling factor, the same or better ESD performance can be achieved as feature size shrinks. Other ways to improve ESD performance in process technologies include those that can reduce snapback voltage, increase junction depth, and increase thermal conduction.

Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap

Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs-AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic transceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of future CMOS technology.