Scaling Circuit Research Articles

A high-light-load-efficiency hysteresis-controlled buck converter with adaptively clocked hysteresis dynamic comparator for IoT applications

A hysteresis-controlled (HC) buck converter with an adaptively clocked hysteresis dynamic comparator (ACHDC) is proposed to improve the conversion efficiency at light load. In contrast to the conventional HC buck converter, a comparator with enabled signal is applied to replace the continuously-on comparator, resulting in significantly reduced static power consumption from the comparator. Additionally, the converter employs an adaptive clock scaling circuit (ACSC) for the dynamic comparator, enabling it to achieve high conversion efficiency across a load current range of 1 μA to 20 mA, with minimal deterioration in ripple voltage. To generate the clock signal, a leakage-based oscillator with dual regulation of capacitance and current is designed. Simulation results demonstrate that the proposed buck converter achieves a peak efficiency of 94.83 % and maintains an efficiency of at least 86.47 % over the entire load range.

Optimization of the 3D multi-level SOT-MRAMs

With the development of electronic technology, semiconductor memory is gradually shifting toward smaller area with less power consumption. SOT-MRAM is one of the competitive substitutes for DRAM and SRAM due to its superior endurance and switching speed. In contrast to STT-MRAM, the separation of read and write routes allows SOT-MRAM to have a lower error rate and higher lifetime, but this comes at the expense of the memory density. In recent years, vertical integrated circuits have relied on TSV to complete 3D stacking to ease the pressure of Moore's Law on scaling circuits. SOT-MRAM can take advantage of 3D stacking to reduce power and latency. More importantly, the density of SOT-MRAM can be improved at the same time. In the paper, simulation is conducted based on DESTINY, with the TSV model supplemented to NVSIM to evaluate the performance of MRAM 3D structures. The 3D SOT-MRAM structure in DESTINY can be implemented with a bus layer and interconnect structure between layers, which greatly reduces the expense of area. However, the 3D structure requires a more complex interconnect structure to truly meet the requirements of high density. For this reason, 3D model of unit interconnection using TSV is presented in the paper. Memory has several components, of which the memory array is the one with the largest area share. This paper explores the spatial structure of the array and proposes a new model which allows more complex interconnect structures to be accomplished on the same area.

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques

Critical path replica (CPR) is a widely used technique in synchronous digital circuit design. However, the existing CPR technique cannot accurately reflect the timing of the circuit due to local process variations (LPV). An improved CPR technique based on load capacitance matching (LCM) is proposed in this paper, which can track critical path delay across wide voltage range. The impact of LPV is simulated under wide voltage range, and a configurable delay line is designed to eliminate the effect of LPV. Furthermore, a low overhead mixed-threshold transition detector (TD) circuit is also proposed to monitor timing violations of the replica path, which generate an ‘error’ signal used to dynamically regulate the chip’s operating voltage. The proposed techniques are implemented on a CORDIC chip using the 55-nm CMOS process. Simulation results show that in the near-threshold voltage (NTV) region, the supply voltage can be reduced from 0.8 to 0.6 V, enabling a maximum of 42.6% power saving at the TT corner, 25°C with lesser than 1% area overhead as compared to the baseline design.

A Low Threshold Voltage Ultradynamic Voltage Scaling SRAM Write Assist Technique for High-Speed Applications

With the percentage of embedded SRAM increasing in SoC chips, low-power design such as the near-threshold SRAM technique are getting increasing attention to reduce the entire chip energy consumption. However, the descending operating voltage will lead to longer write latency and a higher failure rate. In this paper, we present a novel low Vth ultradynamic voltage scaling (UDVS) 9T subthreshold SRAM cell to improve the write ability of SRAM cells. The proposed Low Vth UDVS SRAM cell is demonstrated with a low threshold voltage speed-up transistor and an ultradynamic voltage scaling circuit implemented in 16 nm low-leakage CMOS technology. This wide supply range was made possible by a combination of circuits optimized for both subthreshold and abovethreshold regimes. This write assist technique can be operated selectively to provide write capability at very low voltage levels while avoiding excessive power overhead. The simulation findings reveal that with 16 nm technology, the write ability is improved by 33% over the normal case at 0.9 V supply voltage.

Principle and Application of Frequency-Domain Characteristic Analysis of Fractional-Order Memristor.

Scaling fractional-order memristor circuit is important for realizing a fractional-order memristor. However, the effective operating-frequency range, operation order, and fractional-order memristance of the scaling fractional-order memristor circuit have not been studied thoroughly; that is, the fractional-order memristance in the effective operating-frequency range has not been calculated quantitatively. The fractional-order memristance is a similar and equally important concept as memristance, memcapacitance, and meminductance. In this paper, the frequency-domain characteristic-analysis principle of the fractional-order memristor is proposed based on the order- and F-frequency characteristic functions. The reasons for selecting the order- and F-frequency characteristic functions are explained. Subsequently, the correctness of the frequency-domain characteristic analysis using the order- and F-frequency characteristic functions is verified from multiple perspectives. Finally, the principle of the frequency-domain characteristic analysis is applied to the recently realized chain-scaling fractional-order memristor circuit. The results of this study indicate that the principle of the frequency-domain characteristic analysis of the fractional-order memristor can successfully calculate the fractional-order memristance of the chain-scaling fractional-order memristor circuit. The proposed principle of frequency-domain characteristic analysis can also be applied to mem-elements, such as memristors, memcapacitors, and meminductors. The main contribution of this study is the principle of the frequency-domain characteristic analysis of the fractional-order memristor based on the order- and F-frequency characteristic functions.

Circuit Implementation of Variable-Order Scaling Fractal-Ladder Fractor with High Resolution

Extensive research has been conducted on the scaling fractal fractor using various structures. The development of high-resolution emulator circuits to achieve a variable-order scaling fractal fractor with high resolution is a major area of interest. We present a scaling fractal-ladder circuit for achieving high-resolution variable-order fractor based on scaling expansion theory using a high-resolution multiplying digital-to-analog converter (HMDAC). Firstly, the circuit configuration of variable-order scaling fractal-ladder fractor (VSFF) is designed. A theoretical demonstration proves that VSFF exhibits the operational characteristics of variable-order fractional calculus. Secondly, a programmable resistor–capacitor series circuit and universal electronic component emulators are developed based on the HMDAC to adjust the resistance and capacitance in the circuit configuration. Lastly, the model, component parameters, approximation performance, and variable-order characteristics are analyzed, and the circuit is physically implemented. The experimental results demonstrate that the circuit exhibits variable-order characteristics, with an operational order ranging from −0.7 to −0.3 and an operational frequency ranging from 7.72Hz to 4.82kHz. The peak value of the input signal is 10V. This study also proposes a novel method for variable-order fractional calculus based on circuit theory. This study was the first attempt to implement feasible high-resolution continuous variable-order fractional calculus hardware based on VSFF.

Differential Propagation Delay Measurement of RSFQ Library Cells Using Ring Oscillators

Performing comprehensive timing characterization of library cells and establishing their model-to-hardware correlation are essential for building robust integrated circuits and scaling circuit complexity. To measure the propagation delay of fabricated library cells, we have designed a differential delay measurement scheme using SFQ ring oscillators. The reference and design-under-test (DUT) rings are designed using circuit elements that are either common to both rings or are of nominally similar design, except for the DUT. By inserting a single pulse in the ring, the oscillation period is measured using two methods: (1) direct voltage measurement, and (2) frequency measurement using a frequency divider followed by an SFQ-to-DC converter. Subtracting delay of the two rings gives us the propagation delay of the DUT. A 1 cm by 1 cm chip and another 5 mm by 5 mm chip, incorporating stand-alone ring oscillator test structures for different library cells, have been fabricated in the MIT-LL SFQ5ee process. The chips also contain test circuits to validate two variants of the input/output multiplexing scheme that facilitate reducing the pads requirement. Two copies of a chip with fifteen DUTs were tested. The measured and simulated results for the voltage and frequency of the ring are compared. The simulations account for critical current density ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> ) and sheet resistance (Rs) fabrication parameters. In addition, we have used the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> as a single free parameter to get a better matching with measurement results. For one of the chips, a 15% higher <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> in simulations results in better matching with measured frequency results for all the DUTs. For example, the discrepancy between simulated and measured DUT ring frequency for the NOT cell was reduced from 19% to 1% when the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_c</i> was changed from nominal to 15% higher in simulations. Detailed measurement and simulation results for several DUTs are presented.

Scaling up and down of 3-D floating-point data in quantum computation

In the past few decades, quantum computation has become increasingly attractive due to its remarkable performance. Quantum image scaling is considered a common geometric transformation in quantum image processing, however, the quantum floating-point data version of which does not exist. Is there a corresponding scaling for 2-D and 3-D floating-point data? The answer is yes. In this paper, we present a quantum scaling up and down scheme for floating-point data by using trilinear interpolation method in 3-D space. This scheme offers better performance (in terms of the precision of floating-point numbers) for realizing the quantum floating-point algorithms than previously classical approaches. The Converter module we proposed can solve the conversion of fixed-point numbers to floating-point numbers of arbitrary size data with p+q qubits based on IEEE-754 format, instead of 32-bit single-precision, 64-bit double-precision and 128-bit extended-precision. Usually, we use nearest-neighbor interpolation and bilinear interpolation to achieve quantum image scaling algorithms, which are not applicable in high-dimensional space. This paper proposes trilinear interpolation of floating-point data in 3-D space to achieve quantum algorithms of scaling up and down for 3-D floating-point data. Finally, the quantum scaling circuits of 3-D floating-point data are designed.

SFQ Bias for SFQ Digital Circuits

Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing techniques already encounter serious challenges for scaling circuits above several hundred thousand junctions. In this work, we propose a novel AC-based biasing scheme for RSFQ-type logic families requiring DC bias. The major step toward this scheme is a superconducting AC/DC rectifier which we introduced at ASC 2014. We proposed to connect the rectifiers to “payload cells” via superconducting inductors with large inductance in order to reduce parasitic effects of flux quantization. Recently, we discovered that this powering scheme works even better at a much lower value of the inductance, when it is just sufficient to hold only one or two flux quanta in the inductive loop between the converter and the payload. In this case, flux quantization in the loop becomes beneficial because the value of current fed into the payload is defined by the value of the coupling inductance. Therefore, our AC/SFQ converter powers the payload cell by single flux quanta rather than by DC current. Such mode of operation is extremely energy efficient because energy is used only to recover the flux quantum consumed by the cell during the logic operation. We present designs of AC/SFQ converters comprising an AC/DC rectifier and a current conditioning circuit which we termed an SFQ filter. We also present test results and demonstrate AC/SFQ powering a payload circuit using circuits fabricated in a new, 150-nm node of Lincoln Laboratory fabrication technology using self-shunted Nb/AlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -Al/Nb Josephson junctions with 600 μA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> critical current density and 200 nm minimum linewidth of inductors.

A Three‐stage programmable impedance scaling circuit

AbstractLarge capacitances are needed for low‐frequency active filters to process biomedical signals. The large capacitance can be implemented on a chip by an impedance scaling circuit. However, the characteristics of the circuit are affected by process variations. Then, we have proposed a digitally programmable impedance scaling circuit using electrical switches to compensate for the process variations. This paper describes a technique to reduce power consumption as compared with the conventional circuit. The proposed circuit is composed of a three‐stage current mirror circuit and electrical switches. To reduce the power consumption, the only signal current is amplified by current mirror circuits and bias current sources. The tuning range of the scaling factor of capacitance is from −35% to +28%, and the tuning accuracy is 1% using six switches. The validity of the proposed method is confirmed by simulations using HSPICE. The power consumption of the proposed circuit is reduced by 51% as compared with the conventional circuit. The proposed circuit is applied to a filter whose cutoff frequency is 100 Hz. From the tuning result, the tuning error is less than 1% for ±30% of ±3σ global variation and ± 3% of ±3σ local variation. © 2021 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

Superconductor Standard Cell Library for Advanced EDA Design

Cell library is the keystone component that enables adoption of advanced electronic design automation (EDA) tools, such as logic synthesis and automatic place-and-route. The EDA tools are essential for scaling circuit complexity by orders of magnitude. We have designed a dual RSFQ/ERSFQ cell library for the MIT-LL SFQ5ee process, that can be used with the superconductor EDA tools suite that is being developed. In addition to satisfying the margins criterion, the performance of each cell has been optimized for Monte-Carlo statistical variations across multiple process corners including minimizing the spread of timing distributions. To enable a digital design flow using HDL simulations with timing back-annotation Liberty files have been developed for multiple process corners, using the load-dependent timing char-acterization. The cells have been designed for a standard height of 40 μm with a grid size of 20 μm. The library provides dedicated tracks for signal and power routing. Multiple independent biases are supported for RSFQ designs. The cells can be interconnected either by abutting or using passive transmission lines. Dedicated moat slots have been provided which are uniformly distributed across the cell. All cells are re-optimized post-layout. The library currently contains 22 unique types of cells. Initial validation of the cell library was performed by designing RSFQ and ERSFQ shift registers for the MIT-LL SFQ5ee fabrication process, which yielded wide operating margins. In addition, we present measurement results for a chip designed and fabricated to characterize several library cells using a multiplexing scheme.

A 1.5–5-GHz Integrated RF Transmitter Front End for Active Matching of an Antenna Cluster

A recently proposed method for realizing frequency-reconfigurable antennas across a wideband is based on adjusting the feed amplitudes and phases of a multiport antenna. In this article, we demonstrate the feasibility of the method, for the first time, with a conjunction of an integrated RF transmitter and a four-element antenna cluster. The implementation performs on-chip amplitude and phase tuning with supply scaling and delay tuning circuits to tune the antenna cluster without requirement of matching network. The antenna cluster is built with four closely spaced antenna elements implemented on a printed circuit board. The transmitter integrated circuit (IC) is implemented in a 28-nm CMOS process with the chip size of 0.85 mm $\times0.95$ mm, including pads. The proof-of-concept implementation demonstrates tunability across a wideband from 1.5 to 5 GHz.

A Glucose Concentration Detector With Wide-Range Converter Used on Livestock

In this study, a glucose concentration detector was used to detect the glucose concentration in the drinking solution of livestock for the first time. The detector comprised a glucose sensor and a proposed wide-range glucose concentration converter. The proposed wide-range glucose concentration converter can linearly convert the concentration of glucose into a duty cycle. To allow them to be used in various glucose sensors, scaling circuits were added to the glucose concentration detector to enable adaptation to the currents generated by glucose sensors. All functions of the glucose sensor and proposed wide-range glucose concentration converter were proved by conducting measurements. The measured input current range of the proposed converter was 30 nA to 3 mA. This ensured that a wide dynamic range of input currents of 100 dB was guaranteed. A glucose concentration in the range of 5%–30% could be detected, and the corresponding duty cycle of the proposed detector was in the range of 4.67%–89.5%. The maximum linear error was −0.75%. The sensitivity of the proposed detector was 3.39%/%, and the chip size was 1.13 $\times$ 1.13 mm2. Finally, an experiment to detect the glucose concentration in the drinking solution of livestock was conducted. The results revealed that the proposed converter was suitable for glucose concentration detection.

Scaling Fractal-Chuan Fractance Approximation Circuits of Arbitrary Order

The scaling fractal-chuan fractance approximation circuit (SFCFAC), which can realize the rational approximation of arbitrary-order fractances and has an excellent approximation performance, is presented in this paper. For an original SFCFAC, the progression ratios of resistance and capacitance are limited to the range 0–1. However, it is possible for the values of both progression ratios to be greater than one. The impedance function of an SFCFAC can be represented by an irregular scaling equation. By solving the scaling equation approximately, the operational order of an SFCFAC can be obtained using both progression ratios as $$\mu = -\lg \alpha /\lg (\alpha \beta )$$ . Therefore, the SFCFAC has fractional operational characteristics, which is explained in theory. Oscillation phenomena are inherent to the SFCFAC. It is necessary to learn about these oscillation characteristics. The approximation performance can be improved by adding a series resistor and a series capacitor to the SFCFAC. The corresponding resistance and capacitance are determined by both progression ratios. The optimization has the advantages of simple operation, evident influence, and good practicality, which will make the SFCFAC competitive in future studies. Moreover, the values of the operational order of SFCFACs are extended from $$-1<\mu <0$$ to $$0<|\mu |<2$$ without using inductors, which is feasible for practical applications.

Bilinear interpolation method for quantum images based on quantum Fourier transform

Image scaling is the basic operation that is widely used in classic image processing, including nearest-neighbor interpolation, bilinear interpolation, and bicubic interpolation. In quantum image processing (QIP), the research on image scaling is focused on nearest-neighbor interpolation, while the related research of bilinear interpolation is very rare, and that of bicubic interpolation has not been reported yet. In this study, a new method based on quantum Fourier transform (QFT) is designed for bilinear interpolation of images. Firstly, some basic functional modules are constructed, in which the new method based on QFT is adopted for the design of two core modules (i.e. addition and multiplication), and then these modules are used to design quantum circuits for the bilinear interpolation of images, including scaling-up and down. Finally, the complexity analysis of the scaling circuits based on the elementary gates is deduced. Simulation results show that the scaling image using bilinear interpolation is clearer than that using the nearest-neighbor interpolation.

Scaling fractal-lattice franctance approximation circuits of arbitrary order and irregular lattice type scaling equation

Although Carlson fractal-lattice fractance approximation circuit belongs to the ideal approximation, it can only have operational performance of fractional operator of negative half-order. When series of this circuit increases, the approximation benefit decreases. Even though the fractance approximation circuit of -1/2n (n is an integer greater than or equal to 2) order can be obtained by using nested structures, the structure of this kind of circuit is complicated and fractional operation of arbitrary order cannot be achieved by this circuit. The Liu-Kaplan fractal-chain fractance class, which can be regarded as scaling extension circuits of the Oldham fractal-chain fractance class, has high approximation benefit and can realize operational performance of arbitrary fractional order. Based on analogy, arbitrary order scaling fractal-lattice franctance approximation circuits of high approximation benefit and corresponding lattice type scaling equation can be achieved through respectively making scaling extension to the Carlson fractal-lattice franctance approximation circuit and its normalized iterating equation. There exists the possibility to verify the validity of this scaling extension and scaling fractal-lattice fractance approximation circuits with operational performance of arbitrary order in different ways, including the transmission parameter matrix algorithm, the iterating matrix algorithm and the coefficient vector iterating algorithm. Arbitrary order scaling fractal-lattice franctance approximation circuits can be realized by adjusting both the resistance progressive-ratio and the capacitance progressive-ratio parameters. The approximation benefit of scaling fractal-lattice franctance approximation circuit of arbitrary order is determined by both the scaling factor and the circuit series. The introduced extension benefit function is to be used in performance analyses. Besides, performance comparisons have been made between the Carlson fractal-lattice franctance approximation circuit of five series and the scaling fractal-lattice franctance approximation circuit of negative half-order. With the increasing of the value of the scaling factor, approximation efficiency of the scaling fractal-lattice franctance approximation circuits gradually increases, which are higher than those of the Carlson fractal-lattice franctance approximation circuits. The Carlson fractal-lattice franctance approximation circuit and the scaling fractal-lattice franctance approximation circuit of five series are designed to be used in the active differential operational circuit of half-order to construct experimental testing systems. The approximation performances of both circuits are investigated from the aspects of order-frequency characteristic and F-frequency characteristic. The approximation performance of the scaling fractal-lattice franctance approximation circuit outperforms that of the Carlson fractal-lattice franctance approximation circuit. As the successful application case, the active differential operational circuit designed by the scaling fractal-lattice franctance approximation circuit is used to do the half-order calculus of triangular and square wave signals. This paper is merely an incipient work on scaling fractal-lattice franctance approximation circuits of arbitrary order and irregular lattice type scaling equations.

A Symmetrical Floating Impedance Scaling Circuit with Improved Low-frequency Characteristics

A Symmetrical Floating Impedance Scaling Circuit with Improved Low-frequency Characteristics

Minimum energy point tracking based on adaptive voltage scaling circuit

In order to realize the low-voltage and low-power dissipation designing of digital circuits, minimum energy point tracking (MEPT) based on adaptive voltage scaling (AVS) circuit is proposed in this paper. With process, voltage and temperature and frequency variance, the supply voltage of digital circuits is decreased dramatically by AVS, and equals to minimum voltage point (MVP), and advantageously in reducing dynamic energy consumption. Based on the MVP, in order to effectively decrease energy consumption of digital circuits, minimum energy point (MEP) of digital circuits is searched via comparing energy dissipation under different supply voltage by MEPT. Therefore, the supply voltage and energy consumption of digital circuits are decreased dramatically by the proposed novel circuit. The proposed circuit has been implemented and fabricated in a standard 0.18 μm CMOS process. The experimental results show that, when operating frequency of load keeps 1.319 MHz, the MVP and MEP of load are 425 and 450 mV, respectively. For operation frequency 5.334 MHz, the MEP changes from 625 to 550 mV with the degree of activity of load difference. Comparing with the traditional fixed voltage circuits, the maximum saving 91% of dynamic energy is realized by the proposed circuit.

An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division

A radio telescope analyzes radio frequency (RF) received from celestial objects. It consists of an antenna, a receiver, and a spectrometer. The spectrometer converts the time domain into the frequency domain by an FFT operation. This paper applies an FFT circuit based on nested residue number system (NRNS), which recursively decompose the RNS. It can decompose the MAC unit into circuits with small sizes. In the FFT using the NRNS, a MAC unit is decomposed into 4-bit ones realized by look-up tables of the FPGA. Also, to realize the scaling (truncation) circuit, we propose a constant division algorithm on the FPGA. The truncation is realized by the division of a dynamic range for a subset of moduli. We implemented the proposed NRNS FFT on the Xilinx Inc. Virtex 6 FPGA. Compared with a Xilinx Inc. binary FFT library, although the number of block RAMs (BRAMs) was increased by 38%, in the RNS FFT, the number of LUTs was decreased by 42-45% and the maximum clock frequency was increased by 38-74%. With this technique, we successfully implemented an FFT that satisfied the required size and speed specifications on an available FPGA, since the excessive number of LUTs was the bottleneck of the binary FFT.

Introduction to the special issue on “High performance analog circuits and design methodologies”

This special issue of the SPRINGER Journal of Analog Integrated Circuits and Signal Processing includes a special section composed of four papers related to ‘‘High performance analog circuits and design methodologies’’. They are selected among those presented at the Joint Conference of 4S-2014/2014 International Conference on Analog VLSI Circuits (AVIC 2014). This conference was jointly organized by Vietnam National University HCMC (VNU-HCM) Integrated Circuit Design Research and Education Center (ICDREC) and Institute of Electrical Engineers of Japan (IEEJ) as an event for commemorating the 20 anniversary of VNU-HCM and 10th anniversary of ICDREC. The conference is the successor of the former International Analog VLSI Workshop. Its purpose is to exchange information, ideas and recent research results on analog VLSI circuits and their applications. The first paper, ‘‘An Improvement of the Current– Voltage Conversion Technique in Over-Current Sensing Circuit for Low-Power Low Dropout Linear Voltage Regulators’’, by Ho Quang Tay, proposes a resistance-less over-current sensing circuit using current–voltage conversion technique for CMOS low dropout linear voltage (LDO) regulators with PMOS as pass device. The second paper, ‘‘Delta-Sigma DAC with Jitter-Shaper-Reducing Jitter Noise’’, by Yuki Watanabe et al., describes a novel delta-sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The third paper, ‘‘Design of a Symmetry-type Floating Impedance Scaling Circuits for a Fully Differential Filter’’, by Fujihiko Matsumoto et al., proposes the impedance scaling techniques in order to realize a small-size low frequency active filter. The final paper, ‘‘A Low-Power and Low-Gm Linear Transconductor Utilizing Control of a Threshold Voltage’’, by Takeshi Ohbuchi et al., proposes a linear transconductor that is realized by the scheme that the threshold voltages of the transistors are changed by the attenuated input voltage using body effect and reverse short-channel effect. On behalf of the editorial committee of this special section, we would like to express our great thanks to all the authors of the submitted manuscripts and all the reviewers for their great contribution and helpful effort. We also would like to thank all of the committee members for their valuable effort expended in this editorial work. Finally, we would like to express our special thanks to the Guest Editorial Secretary, Professor Cosy Muto, Nagasaki University and Professor Hiroo Sekiya, Chiba University, and the Advisor, Professor Takeshi Shima, Kanagawa University, for all their contributions and efforts.