Feature scaling in advanced CMOS technology has been slowing down starting at 10 nm node and is expected to stop completely in the next few years. Nevertheless, transistor density scaling is continuing at a Moore’s law pace, driven by DTCO and 3D IC.Transistor dimensions and minimum metal pitch are expected to be massaged down only by 10% to 20% during the next decade. However, both the transistor and the interconnect will continue to evolve and improve both in performance and in variability.Currently, the industry is transitioning from FinFET technology to GAA (Gate All-Around) technology. The next transition, from GAA to the NMOS and PMOS GAA transistors stacked on top of each other (often referred to as CFET (Complementary Field Effect Transistor)) is expected in 8 to 10 years from now.The main methodology for GAA and CFET transistor engineering comes down to bandstructure engineering, where material composition, shape and thickness of different layers, and mechanical stress are engineered to tailor a bandstructure of the channel that maximizes on-state driving strength and minimizes off-state leakage and variability. The key methodology for bandstructure engineering is ab-initio analysis of transistor components and then transfer of the obtained bandstructure to transistor scale analysis to characterize its behavior.For the interconnect engineering, the tight metal pitches and increasingly tall and narrow vias dictate transition from copper to alternative metals, with a preference for the metals that can be etched and selectively grown. The key methodology for interconnect engineering is ab-initio analysis of electron scattering at the interfaces and grain boundaries. The scattering is then converted into interconnect resistance that defines speed and power consumption of the advanced CMOS circuits.This work introduces the concepts of transistor band structure engineering and interconnect scattering engineering and provides illustrations of these methodologies applied to GAA and post-GAA technologies.