SC Integrator Research Articles

SC amplifier and SC integrator with enhanced immunity to capacitor mismatch

Novel switched-capacitor amplifier and integrator with enhanced immunity to capacitor mismatch are presented. Both circuits are based on a capacitor mismatch compensation scheme that the amount of the transferred charge is only dependent on one of the capacitors, instead of the ratio of the two capacitors. The proposed multiply-by-two amplifier requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error caused by capacitor mismatch and provides better power efficiency. Furthermore, the proposed integrator with an accurate gain of one is insensitive to capacitor-mismatch and the input offset voltage of the opamp is removed completely. Finally, Monte-Carlo simulation results are presented to confirm the feasibility of these new techniques, demonstrating its suitability in high-resolution pipelined ADC or sigma-delta modulator.

Answer to Comment on “High performance low-voltage QFG-based DVCC and a novel fully differential SC integrator based on it”

This article tries to answer to comments delivered by Fabian Khateb et. al. about the article “High performance low-voltage QFG-based DVCC and a novel fully differential SC integrator based on it” [1] H. Moradzadeh and S. J. Azhari, IEICE Electron. Express, vol. 5, no. 23, pp. 1017-1023, 2008.

Comment on “High performance low-voltage QFG-based DVCC and a novel fully differential SC integrator based on it”

Comment on “High performance low-voltage QFG-based DVCC and a novel fully differential SC integrator based on it”

IEEE Technology Management Council

There are other non-idealities that have not been modeled here. The gain of the fully differential op amp is dependent on its voltage output. The sampling switches inject charge non-linearly as a function of the input voltage. Both of these non-idealities create harmonic distortion in the modulator output. These have been left out of the model because they do not strongly determine the integrator power. The effect of switch resistance on settling has not been modeled, but including it may show that more op amp power is needed to compensate for the modest increase in the settling time constant. Conclusions This paper demonstrates that a behavioral model, which models charge sharing, slewing, settling, and total thermal noise, can be used to optimize the power of a SC integrator employing a single stage, class A op amp. Information gained from such an optimization can be used to decide whether a different modulator architecture or more complex op amp is needed, or it can be used determine the number of quantizer levels needed in a multibit modulator. Once the power has been optimized, the designer can use the optimization result as a baseline to design the integrator with real devices, discovering where additional power may be needed to accommodate other non-idealities that were not addressed.

Test of a switched-capacitor ADC by a built-in charge sensor

A test methodology for switched capacitor circuits is described. The test approach uses a built-in sensor to analyze the charge transfer inside the circuit under test (CUT). The test methodology is applied to a 10-bit algorithmic analog to digital converter to obtain the static linearity and to the simulated fault coverage figures taking into account a catastrophic fault model. The goodness of the charge sensor has been experimentally evaluated with an SC integrator for fault detection and built-in sensor influence on the CUT performance.

Area-efficient gain- and offset-compensated very-large-time-constantSC integrator

A novel gain- and offset-compensated (GOC) charge-differenciating (CD) SC integrator is presented. The resulting gain, phase and offset errors are considerably smaller than those of previously proposed non-GOC and GOC CD very-large-time-constant (VLT) integrators.

Approach to the design of low-voltage SC filters

A design approach for low-voltage SC filters to be implemented in standard CMOS processes is presented. It is based on simple building blocks which are a clock booster and an SC integrator which uses a single-input amplifier instead of the traditional differential-input amplifier. To validate the proposed approach, a fourth-order elliptic SC low-pass filter was designed using a 1.2 /spl mu/m CMOS process and 1.5 V power supply. The measured frequency response accurately agrees with the simulated one in which an infinite-gain amplifier was considered. When the power supply is set to 1.5 V, the filter has a power consumption of 400 /spl mu/W and occupies a silicon area of 0.8 mm/sup 2/.

Effect of switch resistance on the SC integrator settling time

Using general feedback theory, a model is developed for the switched-capacitor integrator. This model is then used to analyze the effects of sampling and feedback switch resistances on the integrator settling time. If the frequency corresponding to the sampling time constant is less than five times the frequency of the second pole of the amplifier, the integrator settling time will be degraded. The feedback switch resistance has little effect on the integrator settling time for switch resistances up to 50 k/spl Omega/.

Low-voltage fully differential switched-opamp bandpass modulator

The paper deals with the design of a low-voltage bandpass ΣΔ modulator implemented with the switched-capacitor technique. To use standard technology (no low-threshold devices) and without an on-chip voltage multiplier, the switched-opamp technique has been adopted. The basic building blocks for the construction of a ΣΔ modulator (SC integrator, quantiser, and feedback DAC) are proposed in a fully differential version. In addition, they have been improved with respect to those previously reported to give a larger output swing at a higher sampling frequency and without any voltage reference. The validity of the proposed circuits is demonstrated by the realisation of a second-order bandpass ΣΔ modulator operating with a single 1 V supply within a standard 0.5 µm CMOS technology (VTHn = 0.65 V, VTHp = 0.7 V). The modulator operates at a sampling frequency of 1.8 MHz with a full-scale input range of 2 Vpk-pk and achieves a 45 dB dynamic range in a 20 kHz bandwidth.

2 V fully-differential SC integrator in standardCMOS

A 2 V fully-differential SC integrator is developed for a standard double-poly CMOS without the need for clock or supply-voltage multiplication. The common mode at the integrator output is set to maximise the signal swing, and the common mode at the input to the OTA is set at the negative rail, maximising the overdrive on all the switches. Two capacitive common-mode adjustment networks are required to alleviate large leakage currents associated with parasitic junction diodes. A novel CMFB technique is proposed. Simulation results are presented for a 1.2 µm CMOS process.

A high-frequency differential sc integrator with highly accurate gain compensation

A high-frequency differential sc integrator with highly accurate gain compensation

A NEW COMPREHENSIVE PROCEDURE FOR THE EXACT DESIGN OF CANONIC LDI-TYPE SC LADDER FILTERS

A new procedure is given for the exact design of canonic LDI-type SC ladder filters realizing any elliptic discrete-time transfer function, including highpass functions. We show that, in contrast to known exact design procedures, the underlying prototype network should be terminated with so-called half-unit delays in order to preserve the capability of realizing any filter type. We will show, based on such ladder prototypes, simple and stray-insensitive LDI-type SC ladder filters can be derived, which are canonical for any filter type (i.e., every filter pole requires for its realization one stray-insensitive SC integrator without the need for additional amplifiers). Compared to common exact design procedures, simpler SC ladder structures are obtained, in particular, for highpass-type filters. Exact designs of canonic SC highpass ladder filters are presented and compared with corresponding biquad designs.

Synthesis of balanced SC integrator based on bilinear s–z transformation

AbstractTo realize an SC integrator which is a representative fundamental section of a switched‐capacitor filter (SCF), via a balanced circuit is effective for high‐frequency applications. to use SC integrators (to which a bilinear s–z transformation is applied) as an s‐region integrator has many advantages in realizing an SCF.This paper proposes a new circuit which realizes an integration characteristic based on bilinear s–z transformation by using a balanced SC circuit. A computer simulation shows that this circuit has a higher frequency range by a factor of about 2, a smaller influence of the capacitor‐error on the integration characteristic, and a smaller common‐mode gain compared with conventional balanced SC integrators with the same scale of hardware. the operation of the proposed circuit was confirmed experimentally by using discrete components.

Design of state-variable SC filters by means of polynomial transformation

A simple polynomial transformation is presented which permits efficient computation of SC state-variable coefficients directly from Z -domain specifications. The algorithm relies merely upon synthetic division. The technique is applied to synthesize a fourth-order elliptic filter using only forward difference integrators (FDI), or, alternatively, only backward difference integrators (BDI). A specific state-variable topology, the so-called observer canonical form, was chosen; the technique, however, is more generally applicable. The use of a single SC integrator topology permits a significant reduction in the number of switches. Experimental results are presented which demonstrate the practical utility of the method.

Fully differential bilinear integrator for SC filters

A fully differential bilinear SC integrator, which can be used for SC filter realisations, is proposed. It is parasitic-insensitive and particularly useful in SC filters simulating analogue ladder networks. The design of these filters is different from the commonly used ones, and leads to filters with better sensitivity properties than earlier versions. Realisation of a third-order highpass filter, bilinearly transformed from the continuous-time to the discrete-time domain, is shown as an example.

Switched-capacitor integrators with low finite-gain sensitivity

Compensated SC integrator stages are analysed and compared with respect to their sensitivities to finite amplifier gain effects. Simple single-stage amplifiers may be used in such circuits even in highly selective filtering applications. This may allow an extension of the present frequency range of SC circuits.

T-cell SC integrator synthesises very large capacitance ratios

Very large pole/sampling-frequency ratios in SC filters require large capacitance ratios and thus result in inefficient area consumption. The use of a T-cell capacitance network allows one to integrate a very large time constant (VLT) integrator, which is, to the first order, insensitive to op-amp offset.

SC integrator for high-frequency applications

The time discrete integrator is a basic building block for a wide range of SC networks. Owing to the finite bandwidth of the amplifier, most of these networks are limited to applications in the audio frequency range. To overcome this restriction, a simple modification of the integrator circuit is presented, which allows the realisation of integrator-based SC networks at frequencies much higher than the audio range.

Noninverting parasitic-compensated bilinear SC integrator with only one amplifier

A noninverting parasitic-compensated bilinear integrator is presented. For the realisation of the circuit, only one amplifier is needed. A fifth-order lowpass filter, designed using the bilinear transformation and realised with this integrator at the input, is also discussed.

Novel SC integrator realising the bilinear z -transform

A novel SC integrator is designed which does not require the use of operational amplifiers. The sampled-data transfer function is related to that of a continuous-time integrator by the bilinear z-transform. The circuit needs only a simple sample-and-hold circuit at the output and is insensitive to all parasitic capacitances, except those present at the output node.