SC1 Cleaning Research Articles

Optimization of SiC Cleaning Process Based on Zeta Potential

This The SiC is a polar semiconductor that is easy to adsorb particles due to the surface charges, which results in that the RCA process commonly used for silicon cleaning is not good for SiC cleaning, and the technique should be optimized. To check the surface charge of SiC wafers during the cleaning process, this work investigated the adsorption of polystyrene spheres (PS) on SiC epitaxial wafers at different pH values and measured the Zeta potential of the SiC wafers. We analyzed the mechanisms by which the Zeta potential in alkaline (SC1) and acidic (SC2) cleaning solutions affects the adsorption of particles on SiC epitaxial wafers surface. The results showed that both the SiC epitaxial wafers and the particles had a negative Zeta potential in the SC1 cleaning solution and there was an electrostatic repulsion between them. In contrast, in the SC2 cleaning solution, the SiC epitaxial wafers and particles had opposite Zeta potentials, which caused attraction between the wafers and particles. Therefore, based on the analysis of Zeta potential, we proposed an optimized the SiC cleaning process that use SC2 cleaning before SC1 cleaning. We successfully reduced the number of particles attached to the surface of SiC epitaxial wafers by 80.4% than RCA cleaning process by the optimized cleaning process. The optimized cleaning process would have a practical value due to the reduction on the consumption of time and chemical reagents.

Development of a novel wet cleaning solution for Post-CMP SiO2 and Si3N4 films

After CMP, the removal of ceria nanoparticle residues is difficult due to the formation of Ce–O–Si chemical bonds on the SiO2 film surface. After STI CMP, several post-CMP cleaning processes are performed, including the application of PVA brushing and megasonic technologies using conventional cleaning solutions such as SC1, SC2, and SPM. However, more effective post-CMP cleaning technologies are still needed for the fabrication of advanced integrated circuit devices. In this study, we developed a novel post-CMP cleaning solution consisting of tetramethylammonium hydroxide (TMAH), ethylenediaminetetraacetic acid (EDTA), and Disponil to replace existing cleaning solutions. In its non-diluted form, this cleaning solution removed 99.5% of residual particles and 98.3% of ceria residue on an SiO2 film surface, as well as 98.5% of residual particles and 98.1% of ceria residue on an Si3N4 film surface, respectively. At 5 × dilution, it removed 97.8% of residual particles and 97.0% of ceria residue on the SiO2 film surface, as well as 97.8% of residual particles and 96.3% of ceria residue on the Si3N4 film surface, respectively. The effectiveness of this cleaning solution for residual ceria nanoparticles is highly comparable to SC1 and SPM conventional cleaning solutions, even though it is used at a relatively low temperature with less etching. Additionally, AFM of the surface topography showed fewer particles and better surface roughness compared with SC1 and SPM cleaning. Thus, this approach can be used to remove ceria nanoparticles from polished SiO2 and Si3N4 films through increased wettability, slight dissolving of the film, and extremely enhanced repulsive force.

The Impact of Dummy Gate Processing on Si-Cap-Free SiGe Passivation: A Physical Characterization Study on Strained SiGe 25% and 45%

High mobility channel materials like SiGe, Ge and IIIV receive lots of interest in order to enable the continuation of Moore’s path during the upcoming technology nodes. Recently Si-cap-free SiGe passivation with the number of interface states (NIT) down to 2 1011 cm-2 have been demonstrated. [1-3] A clear correlation was established between Ge-content in the SiGe-oxide and NIT. Unfortunately no process information has been provided on how the Ge-oxide-free interlayers were obtained. In a separate study the impact of HF, HCl and SC1 cleaning solution on the SiGe surface and oxide composition was reported. [4] A comparison of SiGe Gate-All-Around (GAA) and FinFET devices using a Si-cap-free SiGe 25% passivation scheme in a replacement metal gate (RMG) integration indicate the device performance is improved by a TMAH (aq) treatment prior to SiGe interlayer formation and high-k deposition. [5] Here the formation of a SiGe wet chemical oxide will be presented. The impact of dummy gate processing on the interlayer composition is reported. Also the impact of a TMAH (aq) treatment prior to chemical oxide formation has been analyzed and will be reported. Blanket strained SiGe 25% and 45% were grown by epitaxy. The SiGe-substrate and -oxide composition were measured by angle-resolved XPS using the Si2p and Ge3d peaks. The Ge3d peak is fitted with three different compounds: elemental Ge, GeO2 and Ge-suboxide. The angle dependence lets us estimate the distribution of the different components with respect to the sample top surface. An concentration increase with increasing angle (relative to the surface normal) indicates the compound is located closer to the sample surface. And reversely a concentration increase with increasing angle indicates the compound is located deeper into the sample. A native oxide was grown on SiGe 25 and 45% by exposing the wafers to the cleanroom air for approx. 1 week. The native oxide was found to be stoichiometric or nearly stoichiometric with a uniform Ge content throughout the oxide for SiGe 25 and 45% respectively. A wet chemical oxide was grown using an ‘imec clean’ [6] having a final O3/HCl (aq) rinse. The wet chemical oxide is Ge-poor compared to the SiGe substrate. No or only a small variation in Ge content of the SiGe-oxide is seen with ARXPS. However the fraction Ge-suboxide decreases with increasing angle, indicating the Ge-suboxide are located deeper within the sample, so closer to the SiGe-oxide/SiGe-substrate interface. The Ge-content of the SiGe-substrate after wet chemical oxidation shows a weak incident-angle-dependence, indicative a limited Ge enrichment of the SiGe substrate towards the SiGe-oxide/-substrate interface. The low Ge content of the SiGe-oxide is attributed to the water solubility of GeO2. The increase in Ge-content towards the SiGe-oxide/-substrate can be (at least partially) attributed to the poor water solubility of Ge-suboxide. The small increase in Ge content of the SiGe substrate can be attributed to the thermodynamically preferred oxidation of Si over Ge. The combined impact of dummy gate deposition, spike anneal and dummy gate removal prior to SiGe interlayer formation was investigated by AR-XPS and SIMS. The temperature used during spike anneal was found to have a significant impact on the Ge-content of the SiGe-oxide formed during an O3-last imec clean. The results will be reported in detail at the conference. The impact of TMAH (aq) on the chemical oxide composition and surface roughness will also be reported. TMAH (aq) was found to improve SiGe device performance. [5] Also the interaction with the subsequent HfO2 deposition will be reported. In summary SiGe is found to behave as a non-linear combination of Si and Ge. In HF-free aqueous solutions, the SiGe oxide composition is a combination of (1) thermodynamically preferred oxidation of Si versus Ge; (2) poor water-solubility of SiO2 and/or its low solubilization rate; and (3) fast dissolution of GeO2 but slow dissolution of Ge-suboxides. [1] CH Lee et al. VLSI 2016. [2] S. Siddiqui et al. presented MRS Spring Meeting 2016. [3] CH Lee et al. IEDM 2016. [4] S.L. Heslop et al. ECS Trans 69 (2015) 287. [5] H. Mertens et al VLSI 2015. [6] M. Meuris et al. Solid State Phenom, July 1995, p. 109. Figure 1

Prevention of Metal Contamination in Sub 50 Nm SC1 Cleaning Process

In this study, we investigated the relationship between particle removal efficiency (PRE), surface etch rate and removal of metal contaminant with various concentrations of SC1 cleaning solution. To identify the relationship between etch rate and the formation of defect, etch depth was measured for various compositions of SC-1 solution by using atomic force microscopy. Si wafers were contaminated with Cu ions and particles by dipping method. Cu precipitate and particles on Si surface were counted by using atomic force microscopy and a dark field optical microscope respectively to evaluate cleaning efficiency of SC1 solutions. The effect of SC1 compositions on Si etching was also investigated. It is observed that with increase in H2O2 concentration both Cu contamination and PRE decreases. This study suggests that the SCl cleaning solution needs to be optimized in order to achieve lower Cu contamination with a high PRE.

Behavior of Nickel Deposition on Silicon Wafers from TMAH and Ammonia based SC1 Cleaning Process

Behavior of nickel adsorption on silicon wafer from SC1 process, based on TMAH, is studied as a function of TMAH concentration, etch rate, residence time in solution. Deposition behavior of nickel on wafer surface is also investigated, from SC1 and dilute hydrochloric acid solution, intentionally contaminated with nickel. Temperature dependence in the behavior of nickel deposition from Ammonia based and TMAH based SC1 solution, is investigated. Finally, characterization of surface-deposited nickel on the wafer surface from the SC1 solution is carried out to provide possible mechanism and nature of deposited nickel.

Prevention of Metal Contamination in Sub 50 Nm SC1 Cleaning Process

The RCA cleaning process is a standard wet cleaning process for removal of contaminants from silicon wafer surface. As well known, the SC1 cleaning solution which consists of a mixture of NH4OH (ammonium hydroxide), H2O2 (hydrogen peroxide) and H2O is an efficient particle removal. Cleaning mechanism of SC1 cleaning solution on particles removal from silicon surface is slightly surface etching and lift off the particles from the Si surface by electrostatic repulsive force between particles and surface. SC1 cleaning process may etch a few angstrom (Å) level of silicon surface. However, metal contaminant which has a high redox potential is critical when bare silicon is exposed. Metal deposition on Si surface is induced by the oxidation reduction reaction between metal ion and Si surface. Metal ion can take electrons from Si surface and are reduced to become metal. Si surface beneath the metal particles is oxidized to become SiO2 and is etched away by OH- in SC1 solution. The metal pit is a form of localized etching that leads to the creation of small hole under the metal. Thus, the etching has a crucial effect on the formation of defects and removal of particles. The etch rate of Si increased with NH4OH concentration whereas it decreased with H2O2 concentration. This indicates that metal pitting increased with NH4OH concentration while H2O2 inhibits it. However, particle removal efficiency (PRE) decreased in high H2O2concentration. Particle removal is affected by etch rate and pH of cleaning solution. For high pH value in the SC1 solution, particles take on a strongly negative charge. The particles are repelled from a Si surface. This electrostatic interaction prevents recontamination by particles to Si surface. Therefore, it is important to optimize SC-1 cleaning process in Si surface cleaning process. In this study, we investigated the relationship between PRE, surface etch rate and removal of metal contaminant with various concentrations of SC1 cleaning solution. The thermally oxidized 200 mm p-type Si (100) wafers were used. To identify relationship between etch rate and formation of defect, etch depth was measured for various composition of SC-1 solution by using atomic force microscopy. The Cu ions were used as a source of metal pitting to making Cu precipitate on Si surface. Si wafers were contaminated with Cu ions and particles by dipping method. Cu precipitate and particles on Si surface were counted using atomic force microscopy and a dark field optical microscope to confirm cleaning efficiency of SC1 solution. Etching of Si wafer surface in SC1 solution was evaluated as a function of composition of SC1 solution. It was shown that Cu precipitates decreased with H2O2 concentration in SC1 solution. But PRE also decreased. It was suggested that H2O2 reduced the formation of Cu precipitates and PRE was dependent of NH4OH concentration. This study proposes cleaning process to minimize Cu precipitates with a high PRE in the optimized SC1 solution. Figure 1

Behavior of Nickel Deposition on Silicon Wafers from TMAH and Ammonia based SC1 Cleaning Process

Adverse affect of surface contamination, including metal, on silicon wafer resulted into continuous evolution of RCA cleaning process.1 Deposition behavior of nickel on silicon wafer from SC1 solution, based on TMAH, is investigated here. A number of process parameters like chemical concentration, process time and temperature on deposition behavior of nickel from SC1 solution are considered. The mechanism of nickel deposition is discussed along with possible formation of some nickel silicide on the surface. Increased level of nickel deposition, as a function of TMAH concentration, from TMAH based SC1 solution is shown in Fig. 1. Time dependency of nickel deposition is carried out by exposing wafer into a nickel-contaminated SC1 solution with incremental period of time. The level of deposited nickel is found to increase with time as shown in Fig. 2. In other words, the non-equilibrium nickel deposition is observed, for the nickel contamination level used here and the period of investigation. Additional nickel deposition study is performed by exposing wafer to TMAH based SC1 and ammonia based SC1 solution as a function of temperatures separately. Higher nickel deposition tendency, from SC1 bath, is observed in TMAH based SC1 solution compared to ammonia-based SC1 solution. Furthermore, the amount of deposited nickel from SC1 solution increases with temperature. The increased level of nickel deposition from TMAH based SC1 solution compared to ammonia- based SC1 solution is likely influenced by the increased stability of the nickel ion in ammonia with the formation of ammonia-nickel complex. 1 Characterization of surface nickel from nickel-contaminated TMAH-based SC1 solution is carried out by dippingsilcon wafers in SC1 that contains 1ppb Nickel for 4.5 min., 9 min and 18 mins. respectively. This is shown in Figure 3. Amount of deposited nickel in chemical oxide was first analyzed with VPD-ICPMS. Subsequently, non-removable surface nickel on the surface was analyzed by ICP/MS following etching with surface with mixture of hydrofluoric and nitric acid. The mechanism of nickel deposition can be considered to proceed by the reduction of Ni+2 ion via electrochemical oxidation of silicon in the alkaline solution.2 In other words the growth of chemical oxide on silicon is due to high redox potential of the SC1 solution containing peroxide. As indicated above the amount of metal oxide is expected to increase with treatment time observed in a similar study with copper.3 Furthermore, the observation of silicon oxide between the deposited nickel and substrate in alkaline solution is observed in an EDX analysis of the interface.4 The oxide layer is proposed to be produced by reaction of oxidized silicon with OH- ion promoted by Ni+2ion. Part of Ni adsorbed on wafer from SC1 (TMAH+H2O2) possibly form nickel silicide, which may be difficult to remove in traditional low pH metal cleaning step. Fig. 1 Amount of Nickel deposited on the wafer following SC1 traetment from SC1 solution with increasing ratio of TMAH to H2O2 concentration. Fig. 2. Nickel adsorption from SC1 solution contaminated with 1 ppb of nickel. Figure 3. Nickel adsorption from TMAH-based SC1 solution and NH3-based SC1 solution as a function of temperature is shown below. Elevated nickel deposition is observed in TMAH-based solution. Figure 4. Removal and non-removal nickel deposited on the wafer surface treated with dilute hydrochloric acid following depostion from from SC1 solution. Increased amount of non-removable nickel is observed with time.

Effect of SC-1 Treatment in Thermal Wall Oxide on Nanoscale STI Gap-Filling by O<sub>3</sub>/TEOS CVD

The SC-1 treatment prior to the O3/TEOS CVD was a very effective method for gapfilling the nanoscale trench of the high aspect ratio by improving the adsorption of TEOS precursors onto the wall oxide. It was found that the interval duration after the SC-1 cleaning was a critical parameter for the contact angle and the gapfill performance of the O3/TEOS CVD.

Macromolecular Contamination on Haze Generation in Amorphous-Silicon Film by CVD: Controlled with Ozonized Water Treatment

Focusing on macromolecular contaminants, we conducted a study on the quality of a film deposited by chemical vapor deposition (CVD). Si wafers (, P100) were coated with a polyethylene oxide (PEO) aqueous solution (, 0.2%) and left at room temperature. They were cleaned with a SC1 solution (, ) for . A film of amorphous silicon (a-Si) was deposited by CVD. Localized defects, commonly called haze, were observed in the resultant film. A thermal-desorption analysis of the residual PEO after the cleaning step revealed the abnormal desorption-peak shift from 400 up to . This shift far beyond the deposition point of is responsible for the haze generation. After the cleaning step, aggregates of residual PEO were observed at several spots on the wafer surface. The Raman spectra of the residues suggested the existence of the peptide links, (CO)–CNH, which may be induced by the reaction of PEOs with during SC1 cleaning. Strong interaction between the peptide links may have caused the aggregation observed. Ozonized water treatment prior to SC1 was found to be effective in removing PEO contaminants and preventing the haze from generating.

Dopant loss of ultrashallow junction by wet chemical cleaning

The loss of the dopant in ultrashallow junction (USJ) by RCA standard clean (SC1) prior to the formation of side-wall spacer is quantified by using transmission electron microscopy (TEM), secondary ion mass spectroscopy, four-point probe, and source/drain extension (SDE) sheet-resistance test structure (SSTS). From the cross-sectional TEM images, the etched depth by one SC1 for n (p)-type SDE was measured to be 1.5nm (0.2nm). From the secondary ion mass spectroscopy profiles, most of the n-type dopant implanted with arsenic at 2keV is expected to be etched-out by four times of SC1 cleaning, while the p-type dopants are immune to SC1 cleaning. We quantified the dopant loss from sheet resistance measurements with the four-point probe and the SSTS. The effect of SC1 cleaning on transistor performance is discussed in terms of on-state current. The dopant loss by SC1 is found to be the most significant factor in process optimization for n-type field effect transistor with USJ.

Surface Preparation for Transistor Performance Improvement in Triple Gate Oxide Integration

Fabrication of current high-performance metal-oxide-semiconductor field effect transistors (MOSFETs) requires a multiple gate oxide integration to obtain different oxide thicknesses and applied voltages. However, channel mobility and drive current are degraded as the number of oxide growth and etching steps increases during the multiple gate oxide integration. In multiple gate oxide integration, a shorter overetch time with a more dilute HF solution for the removal of preexisting oxides exhibits improved surface mobility and transistor drive current resulting from the suppression of surface roughness deterioration. The elimination of SC1 cleaning or the addition of a lower-temperature dilute SC1 cleaning in the pregate cleaning sequence also produces improved transistor mobility. Considering that the addition of SC1 cleaning in the pregate cleaning sequence is needed to remove particles on the surface, the use of a dilute SC1 cleaning may be a realistic method to achieve both improvement of transistor performance and removal of particles. Mobility and drive current of are found to be more sensitive to surface preparation changes than , which may be explained by the closer proximity of electrons to the interface compared to holes.

Control of SC1 Wet Cleaning Process for Nano-Scale Gate Oxide Integrity

The effect of H2O:H2O2:NH4OH (SC1) pre-gate cleaning on the oxide thickness and Si etching were investigated. If the oxide thickness is more than 11 Å, etching of SiO2 is dominant, while the oxidation rate on Si surface is faster than the etch rate of Si, if the oxide thickness is less than 11 Å. The thickness of thin gate oxide is affected by SC1 cleaning and the photoresist removal method in a dual-gate-oxide integrity process. The etch rate of a hydrophobic silicon surface was five times faster than that of a hydrophilic surface in a 50°C 5:1:1 SC1 solution. If the surface was converted into hydrophilic, the etch rate of silicon dropped to 1.0 Å/min, and remained constant with the process time. The etch rate of silicon reflecting the etch rate of chemical oxide is higher than that of the thermal oxide, but lower than that of the plasma enhanced chemical vapor deposition (PECVD) tetra ethyl ortho silicate (TEOS) film.

ZETA Potential Induced Particle Generation in SC2 Cleaning

After etch and photo resist (PR) strip, particle and byproduct removal treatment is inevitable. SC1/SC2 cleaning process is one of the useful wet cleaning processes to remove them. In most cases, the equipment is batch type (25 or 50 wafers dip into bath) in which particles lifted from edge or backside of wafer move into chip easily by the stream of chemical. Especially in the process of film like Si3N4 with high dielectric constant, the particle issue is more serious. Following SC1 cleaning (main chemical is NH4OH), SC2 cleaning (main chemical is HCl) causes particles to be attached to wafer. The lifted particles in SC1 cleaning are attached to wafer strongly by ZETA potential, which is enhanced when the PH of chemical is lower than 4 (PH of SC2 chemical is about 1.3). SC2 cleaning after SC1 cleaning is not desirable process sequence. But, SC2 chemical is useful for removing metal contamination generated in etch equipment during the etch process. Skipping SC2 cleaning is desirable in the process which metal contamination has no impact on. But, if you want to use SC2 cleaning or other acid chemical (PH below 4) for a guarantee of quality of device, it should be processed before SC1 cleaning.

Formation of porous grain boundaries in polycrystalline silicon thin films

Unique polycrystalline silicon (poly-Si) thin films, which were permeable to a concentrated hydrofluoric acid solution through their porous grain boundaries, were investigated to elucidate the formation mechanism of their microstructure. 0.1-μm-thick permeable poly-Si thin films were made through processes of amorphous silicon film formation by low pressure chemical vapor deposition, successive postannealing for crystallization, and excess phosphorus diffusion by a phosphorus oxichloride predeposition. At the grain boundaries, porous microstructures were formed after the films were cleaned in an SC1 solution (a 1:1:5 mixture of NH4OH:H2O2:H2O at 80 °C for 10 min), whereas segregated soluble precipitates observed by a field emission secondary electron microscope were present before the SC1 cleaning. Auger electron microscope revealed that the surface of the precipitates mainly consist of silicon (∼80 at. %) and oxygen (∼20 at. %). As a result of transmission electron microscope observation, it is concluded that enhancement of silicon atom mobility by the phosphorus doping process induced consequent segregation of the soluble precipitates at the grain boundaries.

Accuracy of differential method to distinguish crystal originated particles from light point defects in Czochralski-grown silicon wafers

To distinguish crystal-originated particles (COPs) from light point defects (LPDs) in Czochralski-grown silicon (Si) wafers, we developed a differential method and studied its performance. To distinguish COPs from LPDs, we compared the difference in LPD properties before and after SC-1 cleaning. COP is defined as an LPD whose location does not change and becomes large in size after SC-1 cleaning. COPs obtained by the differential method were directly observed by atomic force microscopy (AFM) and the accuracy of counting COPs was estimated. Under optimum conditions, COP detection exceeded 75%, making the differential method useful for the estimation of COPs in CZ-Si wafers.

PCA Characterization of Residual Subsurface Damage After Silicon Wafer Mirror Polishing and its Removal

Residual subsurface damages introduced by mirror polishing into Si CZ wafers degrade GOI in ULSI MOS devices. A removal of the damage throughout 9 times SC1 cleaning was systematically characterized as correlated between PCA signals measured by noncontact UV/mmwave technique, GOI at 10MV/cm for MOS diodes with a thin gate-oxide thickness of 10nm, surface microroughness Ra measured by AFM. The same characterization was carried out for epitaxial wafers, as reference. Degraded GOI and PCA signal were recovered throughout 3 times SC1 cleaning and did not depend on Ra of 0.1–0.2 nm, which led to that the damage causes the degradation of GOI, but it can be removed by 3 times SC1 cleaning, and the damage depth was about 21nm. Further, the PCA signal well reflects to removal of the damage and degradation of GOI so that it can be a monitor for characterizing the removal and GOI. Direct observation of the damage using OSDA was carried out for the epitaxial wafer polished and SC1 cleaned. The OSDA indicated an image involving straight lines which disappeared after 3 times SC1 cleaning. This gave a direct evidence for catching up it by PCA and existence of residual subsurface damages.

First Observations of 0.1 μm Size Particles on Si Wafers Using Atomic Force Microscopy and Optical Scattering

We have developed a new technique on the basis of an optical scattering phenomenon to link the coordinates of a commercially available wafer inspection system (WIS) to an analyzer with a high precision of ±0.1 μm. This new technique has been installed in a large sample atomic force microscope (AFM) capable of observing wafers of 8 in. size. One of the most remarkable features of this newly developed AFM is the ability to observe the same position on a wafer before and after certain processes. In this paper, we report on the results of the first observations of 0.10 μm size particles such as crystal‐originated particles (COPs) and dusts on a polished (100) CZ‐type Si wafer before and after SC1 cleaning by using the newly developed AFM. It was first found that the 0.10 μm size COPs are inherently juts before SC1 cleaning. After SC1 cleaning, these COPs turned into a deep crystalline pit. These pits run parallel to the 〈110〉 axis of the wafer and have four facets with an angle of 54° with respect to the surface of the wafer. Second, the actual size of the dust particles were found to be much bigger than expected by using the WIS. The difference is considered to be attributed to the correction method used in the WIS by comparing with 0.10 μm in size polystyrene latex standard particles. These results show that the AFM combined with an optical scattering system is useful in the evaluation of 0.1 μm sized particles as well as in the wafer cleaning process.

Noncontact Photoconductivity Amplitude Technique to Characterize Polishing- and Slicing-Induced Residual Damage in Si Wafers

ABSTRACTThe photoconductivity amplitude (PCA) technique with UV laser carrier excitation has been proposed to characterize surface property and subsurface damage. Combining this new technique with mechanochemical polishing has determined the depth profile of the slicing-induced residual damage. Combining SC1 cleaning with this technique allows to determine the depth profile of residual damage induced by mirror polishing. This result leads that the mirror polishing-induced damage can be removed by the SC1 cleaning.

Recent Advances in Wet Processing Technology and Science

For the cleaning of silicon substrates, a mixture of an oxidizing and an etching agent is often used. One of the first successful mixtures (1970) is the well known APM or SC-1 cleaning (NH4OH/H2O2/H2O) (1). Since then, other mixtures (oxidizing agent/etching agent) such as HNO3/HF (2), H2O2/HF (3) were developed. For the cleaning of silicon substrates, a mixture of an oxidizing agent and an etching agent always results in good particle performance, since the Si under the particles is continuously oxidized and etched simultaneously (2,3).

Improvement of Gate Oxide Integrity Characteristics in CZ-Grown Si Crystals by H2 annealing

ABSTRACTThe mechanism of improvement in gate oxide integrity (GOI) characteristics by H2 annealing in CZ-grown Silicon wafers was investigated. Grown-in defects that are considered to degrade GOI and which can be detected correlatively as 0.1 μm level size pits appearing after SC-1 cleaning, decrease drastically by H2 annealing, while other inert gases, i.e., N2 and Ar, do not exhibit such effect. Besides, H2 annealing shrinks or extinguishes oxygen precipitates significantly, while other gases do not. On the other hand, oxygen outdiffusion is exactly the same among H2, N2 and Ar annealing. From these results, it was concluded that the dominant mechanism for GOI characteristics improvement by H2 annealing is due to decomposition of the grown-in defects having Si-O bonding by the reduction reaction between Si-O bonding and hydrogen, and not due to a mere thermal decomposition enhanced by oxygen outdiffusion.