SAR ADC Research Articles

Разработка алгоритмов калибровки аналого-цифровых преобразователей с использованием математической модели на примере АЦП последовательного приближения

Разработка алгоритмов калибровки аналого-цифровых преобразователей с использованием математической модели на примере АЦП последовательного приближения

Arithmetic Tracking Adaptive SAR ADC for Signals With Low-Activity Periods

This paper introduces a novel arithmetic tracking algorithm for successive approximation ADCs, and presents its analysis. The algorithm utilizes low activity signal periods to cut the ADC energy dissipation by reducing the number of required bit-cycles. The approach determines the required step size, and bypasses conversion cycles when signal activity is low, without compromising the precision or sampling rate. The required first-order predictions and boundary checkings are performed with simple digital circuits. A lowered number of cycles paired with reduced voltage variations across DAC capacitors yields power savings. The solution has been simulated in a 90 nm CMOS process using HSPICE, demonstrating a 10-bit tracking SAR ADC. The proposed ADC was examined with low activity signals such as EEG, ECG, etc. The results predict from $5.8~\mu \text{W}$ to $27.6~\mu \text{W}$ dissipation when the sampling rates range from 32 kHz to 800 kHz, respectively.

An Ultrasonic Echo-signal Based Digital Background Calibration for Pipelined SAR ADC

An Ultrasonic Echo-signal Based Digital Background Calibration for Pipelined SAR ADC

2nd-Order shaping technique of the DAC mismatch error in noise shaping SAR ADCs

A switching scheme to realize 2nd-order digital-to-analog converter (DAC) mismatch error shaping (MES) technique in the high-resolution noise shaping successive approximation register analogue-to-digital converters (NS SAR ADCs) is proposed. By feeding back the combination of the least significant bit (LSB) DAC mismatch errors in two previous cycles, the DAC mismatch error is 2nd-order shaped. The scheme only requires an extra reference voltage and triples LSB DAC, which leads to simple control logic. According to the simulation, the spurious-free dynamic range is improved 10 dB more than the 1st-order MES.

An Integrated Multi-Channel Biopotential Recording Analog Front-End IC With Area-Efficient Driven-Right-Leg Circuit.

A multi-channel biopotential recording analog front-end (AFE) with a fully integrated area-efficient driven-right-leg (DRL) circuit is presented in this paper. The proposed AFE includes 10 channels of low-noise capacitive coupled instrumentation amplifier (CCIA), one shared 10-bit SAR ADC and a fully integrated DRL to enhance the system-level common-mode rejection ratio (CMRR). The proposed DRL circuit senses the common-mode at the CCIA output so that the AFE gain is reused as the DRL loop gain. Therefore, area efficient unit-gain buffer with small averaging capacitors can be used in DRL circuit to reduce the circuit area significantly. The proposed AFE has been implemented in a standard 0.18-μm CMOS process. The DRL circuit achieved more than 85% chip area reduction compared to the state-of-art on-chip DRL circuits and maximum 60 dB enhancement to system-level CMRR. Measurement results show high/low AFE gain of 60 dB/54dB respectively with 1 μA/channel current consumption under 1.0 V power supply. The measured AFE input-referred noise in 1 Hz - 10k Hz range is 4.2 μVrms and the maximum system-level CMRR is 110 dB.

A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC

This paper proposes a low power 10-bit 2b/cycle time and voltage based-successive approximation register (SAR) analog-to-digital converter (ADC). At low supply voltage, there will be a significant difference in comparator decision time for different input voltages. By taking advantage of the fact, this ADC converts the reference voltage to the corresponding comparator decision time, achieving 2b/cycle quantization to improve the conversion speed. In addition, by obtaining reference delays with duplicated circuits and using non-binary capacitor arrays, the ADC can tolerate process, voltage and temperature (PVT) variations and decision errors. To validate these concepts, a 10-bit 2MS/s SAR ADC is designed using 130nm CMOS process with 0.5V power supply voltage. Measured results show that the ADC can work normally from 0.5V to 1V supply voltage, with the sampling rate increasing from 2MS/s to 32MS/s. The ADC achieves an SNDR (signal-to-noise distortion ratio) of 56.7dB, corresponding to an ENOB (effective number of bits) of 9.13 bits and consumes $3.4\mu \text{W}$ , resulting in a figure of merit (FoM) of 3.03 fJ/c.-s at 0.5V supply voltage and 2MS/s sampling rate.

A 4 bit highly energy and area efficient SC SAR ADC based on a combinational technique with reduced reset energy

A combinational method, based on hybrid and junction splitting techniques, is used to realize a 4 bit high energy efficient SC SAR ADC. The hybrid switching scheme is very energy efficient in which the first three comparison cycles do not consume any energy. In junction split technique, the total value of capacitors does not remain constant. Rather capacitors are appended as bits are being determined successively. The present method combines the features of these two methods to realize an even more energy efficient SC SAR ADC. Reset energy, in some cases, can seriously impact the overall efficiency of a SC SAR ADC. A study has been made about the normal reset energy and two step reset energy for the different cases. A table has been drawn to show the overall energy efficiency for normal conversion, conversion with single step reset and lastly conversion with two step reset for all the architectures.

A 0.6-V 9-bit 1-MS/s Charging Sharing SAR ADC With Judging-Window Switching Logic and Independent Reset Comparator for Power-Effective Applications

This brief presents a 9-bit energy-effective charge sharing (CS) SAR ADC by using judging window switching logic. The power consumption of the DAC is greatly reduced when the signal is within a predefined small window. An independent reset technique is properly designed to improve the power efficiency of the latch comparator. Fabricated in a 0.18-μm process, the 9-bit ADC occupies a die area of 0.15 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Through optimized design, a maximum 75% and 37% power savings are obtained in the DAC and comparator, respectively. The measured DNL and INL are less than +0.56/-0.59 LSB and +0.83/-0.74 LSB. Operating at 1 MS/s, the CS ADC provides an SNDR up to 54.0 dB and SFDR up to 75.6 dB for a full-scale signal @ 0.422 MHz while consuming 2.65 uW from a 0.6-V power supply, resulting in a figure of merit (FoM) of 6.4 fJ/conversion step. Thanks to the judging window power can scale down to 1.74 uW for further power savings for small amplitude signals.

Balanced sampling switch for high linearity and a wide temperature range in low power SAR ADCs

This Letter proposes a balanced sampling switch technique for achieving high linearity and a wide temperature range. The proposed technique reduces the V DS of the NMOS sampling switch for reducing the leakage current through the switch during the hold mode. This operation is implemented by a mini capacitive digital-to-analogue converter (C-DAC) that mimics the main C-DAC used for main SAR conversion. The proposed sampling switch is applied to a 10-bit, 0.5 V SAR ADC with 5 Msample/s and verified by comprehensive simulation. Compared to the conventional sampling switch without the mini C-DAC, the proposed switch improves SFDR and SNDR by 27.52 dBc and 11.8 dB, respectively, at the FF corner and 120°C.

Energy-Efficient Motion-Triggered IoT CMOS Image Sensor With Capacitor Array-Assisted Charge-Injection SAR ADC

We propose a low-power image sensor with a motion-based triggering feature for the Internet of Things (IoT) applications. The sensor supports the near-pixel [within analog-to-digital converter (ADC)] motion-detection mode run on a heavily subsampled frame (32 $\times $ 20 pixels, while consuming only 1.7 $\mu \text{J}$ /frame) to trigger full-array capture only when a significant change has happened in the scene. Also, to maximize energy efficiency and image quality of the sensor, we propose a column-parallel capacitor array-assisted charge-injection SAR ADC that achieves 10b operation with readout noise of 226 $\mu V_{\text {rms}}$ , which can be lowered to 104 $\mu V_{\text {rms}}$ using multiple sampling. The ADC is highly energy efficient with best-in-class energy consumption of 63.6 pJ/frame/pixel and ADC Figure of Merit (FoM) of 14.4 $\mu V_{\text {rms}}\cdot $ nJ in full-array capture mode.

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique

This article presents a reference ripple cancellation technique for high-speed successive approximation register analog-to-digital converters (SAR ADCs) to address the reference voltage settling issue. Unlike prior techniques that aim to minimize the reference ripple, this article proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. To verify the proposed technique, a prototype 10-bit 120-MS/s SAR ADC is fabricated in a 40-nm CMOS process. The proposed ripple cancellation technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL)/differential non-linearity (DNL) by ten times. Overall, the ADC achieves an SNDR of 55 dB with only 3-pF reference decoupling capacitor.

Inherently Accurate Attenuation-Based Digital Calibration of ADC

This paper presents inherently accurate digital calibration of ADC non-linearity, which requires neither absolute accuracy of a signal for calibration nor any modification of ADC core, hence enabling the use of existing ADC IP cores. It only relies on constant attenuation ratio provided by a passive resistive attenuator and hence it is inherently accurate as exemplified by extensive simulations as well as comparison with conventional method. A prototype $0.35\mu \text{m}$ -CMOS cyclic ADC with the on-chip signal generator for calibration has achieved the noise-limited 71.2-dB SNDR after the calibration under the sampling rate of 300 kS/s with 1.0-mW power and 0.087-mm2 chip area. The proposed calibration can be applied to the pipelined and cyclic ADCs with finite-gain non-linear op-amps as well as the SAR ADC.

A −68 dB THD, 0.6 mm2 Active Area Biosignal Acquisition System With a 40–320 Hz Duty-Cycle Controlled Filter

This paper presents a reconfigurable front-end (FE) circuit for acquiring various low-frequency biomedical signals. An energy and area-efficient tunable filter is proposed for adapting the FE bandwidth to the signal of interest. The filter is designed using a switched-R-MOSFET-C (SRMC) technique to realize the needed ultra-low cutoff frequency. An 8-bit SAR ADC, following the filter, quantizes the signal, while the SAR control logic is re-used to accurately program the filter bandwidth from 40 Hz to 320 Hz with a 40 Hz step. The prototype chip includes the complete FE system, formed of an instrumentation amplifier (IA), a programmable-gain amplifier (PGA), and the proposed tunable filter followed by the SAR ADC. Implemented in 0.13 $\mu \text{m}$ CMOS technology, the IC occupies a 0.6 mm2 active area while consuming 6.3 $\mu \text{W}$ dc power from a 2-V supply. Measurement results show a FE gain range of 43–55 dB with an integrated input-referred noise ( ${V_{\text {IRN}}}$ ) of 3.45 $\mu V_{\text {rms}}$ , a 66 dB dynamic range (DR), and a total-harmonic distortion (THD) of −68 dB at an input amplitude of 6 $\text{m}V_{PP}$ . The effective number of bits (ENOB) for the ADC is 7.921 bits at 1-kS/s. In real-time Electrocardiogram (ECG), Electromyography (EMG), and Electroencephalography (EEG) measurements, high-fidelity waveforms are acquired using the proposed FE IC, validating the system’s reconfigurability and high-linearity.

A Four-Step Incremental ADC Based on Double Extended Binary Counting With Capacitive DAC

This brief proposes a discrete-time four-step reconfigurable incremental ADC (IADC) which consists of a first-step SAR conversion, a second-step IADC operation, and double extended binary counting (EBC). While coarse conversion with the 8b SAR ADC is preceded, instead of 8b DAC, 7b capacitive DAC based integrator operation in the IADC becomes available to reduce the chip area and power consumption of amplifier. Additional resolution is achieved by performing the EBC twice, where its conversion time is reduced by using the binary operation with a 7b capacitive DAC. The IADC and the EBC are reconfigured to utilize the same sub-blocks of one amplifier and one comparator, thus reducing silicon area and obtaining high linearity. A prototype ADC is fabricated in a 180-nm CMOS process, and it achieves 179.7 dB FoM and consumes 176 $\mu \text{W}$ .

A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System

In this paper, a low-power detective open-loop dynamic (DeOLD) system buffer codesigned with a SAR ADC that is pertinent for zero-capacitor touch with a display driver integration (TDDI) system is proposed. The proposed DeOLD system buffer not only blocks the supply coupling interference off the ADC but also compensates the lost charge back to the supply by actively detecting the ADC input signal. Its third-harmonic distortion is suppressed to under 70 dB. The dynamic charge sharing technique reduces the power of the charge compensators by 40% compared with the well-known pump squeezing technique. A supply reset (RST) circuit makes up the charge loss and avoids the usage of an unpractical charge compensator to save additional chip area and energy. The system buffer is open loop, which is fast and energy-efficient; furthermore, it is codesigned with a 400-kS/s 10-b SAR ADC. The system buffer provides all voltage sources for the ADC, including the reference, digital, and analog voltages. It consumes 334 nW under a 0.6-V supply. Its active area is only 0.0098 mm2 in 40-nm CMOS technology. It achieves an signal-to-noise and distortion ratio (SNDR) of 55.96 dB, resulting in the Walden figure-of-merit (FoMW) of 1.63 fJ/c.-s.

A Calibration-Free 13-Bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded Op-Amps

This paper presents a calibration-free 13-bit 10-MS/s full-analog successive-approximation-register analog-to-digital converter (SAR ADC) in 40-nm CMOS, which fully utilizes the timing and power budgets in a bit-conversion cycle by eliminating the digital circuits entirely. Continuous-time feedforward cascaded (CTFC) op-amps are proposed to enhance the residue power without the necessity of high-precision quantizers. As opposed to the residue amplifiers (RAs) in multi-step/pipelined ADCs, the CTFC op-amps in the open-loop configuration are implemented with the relaxing gain–bandwidth product (GBW) and without the limitations of accurate gain, precise settling, and voltage swing. Inverter-based regenerative-amplifier (IRA)-based zero-crossing detectors (ZCDs) with self-triggered amplification-to-regeneration (A-to-R) operation are developed to perform serial full-analog SAR bit conversions. The stability in multiple negative feedback (NFB) loops formed by the CTFC op-amps and ZCDs is analyzed and confirmed. The input-referred noise (IRN) and input-referred offset (IRO) in each bit conversion are suppressed by the CTFC op-amps and tolerated by the digital-to-analog converter (DAC) radix and sub-ADC arrangements. The LSB repeating is adopted to entirely cancel out the suppressed IRO mismatches among the bit conversions in the fine ADC. This work occupies an active area of 0.013 mm2 and achieves the Nyquist-rate signal-to-noise-and-distortion ratio (SNDR), spurious-free dynamic range (SFDR), Walden figure-of-merit (FoMw), and Schreier FoM (FoMS) of 67.6 dB, 77.2 dB, 3.3 fJ/conversion-step, and 176.5 dB, respectively.

The Research on SAR ADC Integrated Circuit

Successive approximation ADCs are widely used in low- and medium-speed applications due to their simpler structure, fewer analog blocks, smaller area, and lower power consumption. The successive approximation ADC mainly includes a sample and hold circuit, a DAC, a comparator, a clock circuit, and a SAR register. The rationality is verified by analyzing, designing and simulating each component circuit. For the research of ADC architecture, SAR type is selected and the key circuit is optimized. Using Cadence layout research, the digital part of ADC circuit can be simulated by Quartus II software and Modelsim software, and the hybrid circuit part is simulated by Candance software PSpice A/D. About layout design, some circuits can be further verified with Proteus software.

Development of the full-chain cryogenic readout electronics for the point-contact HPGe detectors

Abstract The paper presents the development of the full-chain cryogenic readout electronics for HPGe detectors for dark matter and neutrino physics experiments. It consists of an ultra-low noise CMOS charge sensitive preamplifier, CR-RC shapers with multiple gains, and a 100 MS/s 10 bits SAR ADC. The preamplifier and ADC ASICs were fabricated in CMOS 350 nm and 65 nm processes respectively, and the shapers were implemented with commercial CMOS components. The integral non-linearity of the cryogenic readout system was measured to be less than 0.09%. An energy resolution of 550 eV ± 20 eV FWHM has been achieved at 122 keV energy peak of 57Co radiation source with optimum DPLMS area-balanced digital filter. The resolution for the pulser signals was also monitored to be 243 eV ± 6 eV FWHM, corresponding to 34 electrons (r.m.s.) ENC noise. Different pulse shapes were captured from the single-site/multi-site events and bulk/surface events The pedestal noise with CR shaper obtained by filtering the baseline signals was measured to be 525 eV ± 23 eV FWHM. The energy threshold for Bulk/Surface discrimination was estimated to be about 2 keV.

An 80.2 dB DR 23.25 mW/Channel 8-Channel Ultrasound Receiver With a Beamforming Embedded SAR ADC

An 8-channel ultrasound receiver compatible with in-probe electronics for 3-D ultrasound imaging is proposed. It has eight analog front-ends for signal conditioning and a beamforming embedded SAR analog-to-digital converter (ADC) for performing both an 8-to-1 analog summation and its digitization in charge mode. By combining the 30-dB programmable gain of the analog front-ends with the 60-dB signal-to-noise ratio of the ADC, the 8-channel receiver achieves the DR of 80.2 dB. The delay is set in increments of 4.17 ns, up to a maximum of 292 ns. Implemented in a 0.18- $ {\mu }\text{m}$ CMOS process, a prototype occupies an active area of 0.525 mm2/channel and draws 23.25 mW/channel at a sampling frequency of 20 MHz.

An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch

An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar speeds and resolutions and more than 2× improvement from the state-of-the-art.