Abstract
This paper introduces a novel arithmetic tracking algorithm for successive approximation ADCs, and presents its analysis. The algorithm utilizes low activity signal periods to cut the ADC energy dissipation by reducing the number of required bit-cycles. The approach determines the required step size, and bypasses conversion cycles when signal activity is low, without compromising the precision or sampling rate. The required first-order predictions and boundary checkings are performed with simple digital circuits. A lowered number of cycles paired with reduced voltage variations across DAC capacitors yields power savings. The solution has been simulated in a 90 nm CMOS process using HSPICE, demonstrating a 10-bit tracking SAR ADC. The proposed ADC was examined with low activity signals such as EEG, ECG, etc. The results predict from $5.8~\mu \text{W}$ to $27.6~\mu \text{W}$ dissipation when the sampling rates range from 32 kHz to 800 kHz, respectively.
Highlights
W ITH the advent of the Internet-of-Things (IoT), minimizing instantaneous and average power consumptions of sensor nodes has attracted much attention 1
While the energy efficiency of digital logic has been improving due to reducing operation voltages and smaller line-widths, the power share of Analog to Digital Converters (ADCs) in sensor nodes can no longer be considered insignificant [2]
Two categories of low activity period energy saving schemes exist for SAR ADCs
Summary
W ITH the advent of the Internet-of-Things (IoT), minimizing instantaneous and average power consumptions of sensor nodes has attracted much attention 1 This is important when aiming at ultra-low power [1] energy scavenging based solutions. If the activity of the comparator and DAC components can be reduced during slow signal change periods, the power dissipation is lowered [12, 13]. Two categories of low activity period energy saving schemes exist for SAR ADCs. A lossy scheme demonstrated by Chiang et al [14] employs an SAR bit cycle bypassing approach that skips resolving the Most Significant Bit (MSB), saving around 12% of power with only 0.017% incorrect conversions. We propose a novel lossless energy saving approach for predictive SAR ADC that requires changes only to the digital part.
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