Runtime Cost Research Articles

BtrPlace: A Flexible Consolidation Manager for Highly Available Applications

The massive amount of resources found in data centers makes it possible to provide high availability to multitier applications. Virtualizing these applications makes it possible to consolidate them on servers, reducing runtime costs. Nevertheless, replicated VMs have to be carefully placed within the data center to provide high availability and good performance. This requires resolving potentially conflicting application and data center requirements, while scaling up to the size of modern data centers. We present BtrPlace, a flexible consolidation manager that is customized through configuration scripts written by the application and data center administrators. BtrPlace relies on constraint programming and an extensible library of placement constraints. The present library of 14 constraints subsumes and extends the capabilities of existing commercial consolidation managers. Scalability is achieved by splitting the data center into partitions and computing placements in parallel. Overall, BtrPlace repairs a nonviable placement after a major load increase or a maintenance operation for a 5,000 server data center hosting 30,000 VMs and involving thousands of constraints in 3 minutes. Using partitions of 2,500 servers, placement computing is reduced to under 30 seconds.

Optimal coverage of an infrastructure network using sensors with distance-decaying sensing quality

Motivated by recent applications of wireless sensor networks in monitoring infrastructure networks, we address the problem of optimal coverage of infrastructure networks using sensors whose sensing performance decays with distance. We show that this problem can be formulated as a continuous p-median problem on networks. The literature has addressed the discrete p-median problem on networks and in continuum domains, and the continuous p-median problem in continuum domains extensively. However, in-depth analysis of the continuous p-median problem on networks has been lacking. With the sensing performance model that decays with distance, each sensor covers a region equivalent to its Voronoi partition on the network in terms of the shortest path distance metric. Using Voronoi partitions, we define a directional partial derivative of the coverage metric with respect to a sensor’s location. We then propose a gradient descent algorithm to obtain a locally optimal solution with guaranteed convergence. The quality of an optimal solution depends on the choice of the initial configuration of sensors. We obtain an initial configuration using two approaches: by solving the discrete p-median problem on a lumped network and by random sampling. We consider two methods of random sampling: uniform sampling and D2-sampling. The first approach with the initial solution of the discrete p-median problem leads to the best coverage performance for large networks, but at the cost of high running time. We also observe that the gradient descent on the initial solution with the D2-sampling method yields a solution that is within at most 7% of the previous solution and with much shorter running time.

A Generalized Closed Form Expression of Directivity of Arbitrary Planar Antenna Arrays

A generalized unique expression for directivity of arbitrary planar antenna arrays having cos <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</sup> θ, v > -1/2 element pattern is derived. Parameters of the new equation, other than the source type, are operating frequency, location, excitation amplitude and excitation phase of each individual element on that structure. Simplicity and compactness of this equation saves the runtime, memory requirement and computer costs. Examples on three array sets have been given to illustrate the effectiveness of this expression. Result of each example is compared with that of referred work, or a standard numerical method to show the computational efficiency.

Simulation-Assisted Formal Verification of Nonlinear Mixed-Signal Circuits With Bayesian Inference Guidance

The pressing need for the verification of analog and mixed-signal (AMS) designs is driven by increased design complexity and the integration of such circuits into SoCs. However, verification of AMS circuits remains a significant challenge. This paper proposes a simulation-assisted formal verification methodology that leverages SMT-based satisfiability techniques to tackle the challenges arising from the inherent analog and/or hybrid nature of AMS systems. Although state-of-the-art SMT solvers, in the worst-case scenario, still have exponential complexity in the number of constraints, the main focus of this paper is to first formally formulate the verification task into an SMT problem, then accelerate the verification by using simulation assistance. To verify the nonlinear dynamics, randomly sampled simulations are first applied to quickly explore the reachable state space, and then a nonlinear SMT solver is invoked to ensure the conservativeness. To achieve optimal efficiency, the tradeoff between the runtime costs of simulation and SMT solving is analyzed by means of a Bayesian inference-based technique that dynamically learns from the simulation history. This paper demonstrates the feasibility and efficacy of the proposed methodology on conservative verification of dynamic properties of nonlinear AMS circuits.

Practical, Lightweight Secure Inclusion of Third-Party Intellectual Property

The security of computing systems relies on trust in hardware. This trust can no longer be assumed due to vulnerabilities in hardware designs. Security methodologies have been proposed for mitigating these threats, offering a variety of security guarantees and wide variance in terms of design-time and runtime costs. From an engineering standpoint it is not clear which of the plethora of solutions should be applied or how they should be implemented. We develop an engineering process for the practical and lightweight inclusion of untrusted third-party hardware design components. We find that by combining previously proposed techniques, we are able to build a microcontroller that uses each design module as if it were untrusted third-party intellectual property. Our experience supports the surprising claim that implementing a chip with untrusted components is not significantly more difficult than implementing a regular one.

Fine-grained fault tolerance using device checkpoints

Recovering faults in drivers is difficult compared to other code because their state is spread across both memory and a device. Existing driver fault-tolerance mechanisms either restart the driver and discard its state, which can break applications, or require an extensive logging mechanism to replay requests and recreate driver state. Even logging may be insufficient, though, if the semantics of requests are ambiguous. In addition, these systems either require large subsystems that must be kept up-to-date as the kernel changes, or require substantial rewriting of drivers. We present a new driver fault-tolerance mechanism that provides fine-grained control over the code protected. Fine-Grained Fault Tolerance (FGFT) isolates driver code at the granularity of a single entry point. It executes driver code as a transaction, allowing roll back if the driver fails. We develop a novel checkpointing mechanism to save and restore device state using existing power management code. Unlike past systems, FGFT can be incrementally deployed in a single driver without the need for a large kernel subsystem, but at the cost of small modifications to the driver. In the evaluation, we show that FGFT can have almost zero runtime cost in many cases, and that checkpoint-based recovery can reduce the duration of a failure by 79% compared to restarting the driver. Finally, we show that applying FGFT to a driver requires little effort, and the majority of drivers in common classes already contain the power-management code needed for checkpoint/restore.

Fine-grained fault tolerance using device checkpoints

Recovering faults in drivers is difficult compared to other code because their state is spread across both memory and a device. Existing driver fault-tolerance mechanisms either restart the driver and discard its state, which can break applications, or require an extensive logging mechanism to replay requests and recreate driver state. Even logging may be insufficient, though, if the semantics of requests are ambiguous. In addition, these systems either require large subsystems that must be kept up-to-date as the kernel changes, or require substantial rewriting of drivers. We present a new driver fault-tolerance mechanism that provides fine-grained control over the code protected. Fine-Grained Fault Tolerance (FGFT) isolates driver code at the granularity of a single entry point. It executes driver code as a transaction, allowing roll back if the driver fails. We develop a novel checkpointing mechanism to save and restore device state using existing power management code. Unlike past systems, FGFT can be incrementally deployed in a single driver without the need for a large kernel subsystem, but at the cost of small modifications to the driver. In the evaluation, we show that FGFT can have almost zero runtime cost in many cases, and that checkpoint-based recovery can reduce the duration of a failure by 79% compared to restarting the driver. Finally, we show that applying FGFT to a driver requires little effort, and the majority of drivers in common classes already contain the power-management code needed for checkpoint/restore.

Reducing instruction bit-width for low-power VLIW architectures

VLIW (very long instruction word) architectures have proven to be useful for embedded applications with abundant instruction level parallelism. But due to the long instruction bus width it often consumes more power and memory space than necessary. One way to lessen this problem is to adopt a reduced bit-width instruction set architecture (ISA) that has a narrower instruction word length. This facilitates a more efficient hardware implementation in terms of area and power by decreasing bus-bandwidth requirements and the power dissipation associated with instruction fetches. In practice, however, it is impossible to convert a given ISA fully into an equivalent reduced bit-width one because the narrow instruction word, due to bit-width restrictions, can encode only a small subset of normal instructions in the original ISA. Consequently, existing processors provide narrow instructions in very limited cases along with severe restrictions on register accessibility. The objective of this work is to explore the possibility of complete conversion, as a case study, of an existing 32-bit VLIW ISA into a 16-bit one that supports effectively all 32-bit instructions. To this objective, we attempt to circumvent the bit-width restrictions by dynamically extending the effective instruction word length of the converted 16-bit operations. Further, we will show that our proposed ISA conversion can create a synergy effect with a VLES (variable length execution set) architecture that is adopted in most recent VLIW processors. According to our experiment, the code size becomes significantly smaller after the conversion to 16-bit VLIW code. Also at a slight run time cost, the machine with the 16-bit ISA consumes much less energy than the original machine.

Trust System Design Optimization in Smart Grid Network Infrastructure

The imposed communication network brings more vulnerabilities to the evolving smart grid. Therefore, defensive techniques such as intrusion detection will need to be deployed in this already complicated system. Deployment and runtime cost due to the defensive trust systems will affect the original function of smart grid system without careful planning and design. This paper is an effort to address this important issue. In particular, the set packing algorithm is used to optimize the placement of the trust nodes of the defensive system in the multiple layer architecture of the smart grid. After the trust nodes are placed, a trust node aware optimal routing algorithm is used to find the least cost routing in the communications of the nodes. Also, an algorithm to identify new trust node(s) is presented to address the fault tolerance requirement of the smart grid system. Simulation results demonstrate that our approach is promising by providing secure, efficient, and reliable communications in the smart grid network.

Development and Validation of a Simple and Efficient RPLC Method for Analysis of Captopril, Metformin, Pioglitazone and Glibenclamide in API, Formulations and Human Serum

The association between the use of ACE inhibitors and the incidence of hypoglycemia is controversial. A recent study reported that 14% of all hospital admissions for hypoglycemia might be attributable to ACE inhibitors. In this paper, a novel, precise, specific, accurate and rapid reversed-phase high performance liquid chromatographic method was developed, optimized and validated for determining captopril and hypoglycemic (metformin, pioglit azone and glibenc lamide) in bulk, pharmaceutical formulations and human serum with the best chromatographic peak resolution, reduced run time and low cost of analysis. The method was validated according to the US Food and Drug Administration (FDA) and ICH guidelines for the parameters: specificity, stability, limits of detection (LLOD), limits of quantification (LLOQ), linearity, accuracy, precision and recovery. This method showed the best resolution by using Hypersil ODS,C18 (150×4.6 mm, 5 micron) column using mobile phase, methanol: water (70: 30 v/v) adjusted to pH 3 via ortho phosphoric acid 85% with flow rate of 1 mLmin -1 at ambient temperature and wavelength of 230 nm. The signal-to-noise ratio (S/N) was employed as a quality measurement. This tool permits to establish the influence of some selected factors (methanol: water ratio, pH, and flow rate) on two responses (peak areas and retention time). The LLOD and LLOQ values for CAP, MET, PGL and GLB were found to be 2.3, 1.5, 2.3 and 2.3 and 0.7, 0.4, 0.7, and 0.7 μgmL-1 respectively. Calibration curves were linear in the concentration range of 2.5-100 μgmL -1 for hypoglycemic and captopril with regression coefficient (r 2 ) value of 0.999 for all drugs. The data for accuracy, precision and recovery were within the FDA limits. Intra ad inter-day precision and accuracy results were 98.0 to 102%. Retention time for captopril was found to be 3.3 minute and for metformin, pioglitazone and glibenclamide 2.4, 2.8, 7.2 minutes respectively. Proposed method was selective, precise and accurate short time analysis therefore can be used for routine, quality control and clinical study. This is the first full report of a method for the simultaneous determination of these four drugs: captopril , metformin, pioglita zone and glibenclamide in API, formulations and serum. The newly developed method is useful for future routine analysis of these drugs and could be used in therapeutic drug monitoring and adherence to medicine studies, which would be helpful in decision making regarding treatment change in combination therapies.

Efficient Certificate-Based Blind Signature Scheme without Bilinear Pairings

Blind signature is a well-known cryptographical technique used to construct some advanced applications for the consideration of user privacy. In this work, we propose the first efficient certificate-based blind signature scheme that follows the idea of Certificate Based Encryption (CBE) presented by Gentry in EuroCrypt 2003. The security of our scheme is based on the elliptic curve discrete logarithm problem over a finite field. In addition, our scheme does not require any pairing operations which is regarded as cosely operations compared to other operations. Compared with the other secure blind signature scheme, our scheme enjoys shorter signature length, less running time and operation cost. So it can be used widely, especially in low-bandwidth communication environments such as wireless cooperative networks.

Development and validation of a high performance chromatographic method for determining sumatriptan in niosomes

In this paper, a novel, precise, specific, accurate and rapid reversed-phase high performance liquid chromatographic method was developed, optimized and validated for determining sumatriptan succinate in niosomes with the best chromatographic peak resolution, reduced run time and low cost of analysis. The formulation has been previously optimized in terms of composition and preparation technique to obtain a high drug encapsulation efficiency and adequate vesicle size distribution.This method showed the best resolution by using Spherisorb® OSD2 C18 column (250mm×4.6mm, 5μm) using phosphate buffer (0.05M):acetonitrile (80:20, v/v; pH adjusted to 6.0) as a mobile phase at a flow rate of 1mL/min and wavelength of 214nm.The main objective of this research was to demonstrate the robustness of the reversed-phase HPLC method development by applying the Taguchi robust methodology. The signal-to-noise ratio (S/N) was employed as a quality measurement. This tool permits to establish the influence of some selected factors (acetonitrile:phosphate ratio, pH buffer, oven temperature and flow rate) on two responses (peak areas and retention time). On the basis of the results obtained, we can conclude that this analytical method was robust for all the factors studies, as exception of the flow rate, where the higher quality was obtained for the fewer values (0.8mL/min). Therefore, this parameter must be carefully controlled when this method was employed, to avoid any modification in the peak areas overall.

Randomized Instruction Injection to Counter Power Analysis Attacks

Side-channel attacks in general and power analysis attacks in particular are becoming a major security concern in embedded systems. Countermeasures proposed against power analysis attacks are data and table masking, current flattening, dummy instruction insertion and bit-flips balancing. All these techniques are either susceptible to multi-order power analysis attack, not sufficiently generic to cover all encryption algorithms, or burden the system with high area, run-time or energy cost. In this article, we propose a randomized instruction injection technique ( RIJID ) that overcomes the pitfalls of previous countermeasures. RIJID scrambles the power profile of a cryptographic application by injecting random instructions at random points of execution and therefore protects the system against power analysis attacks. Two different ways of triggering the instruction injection are also presented: (1) softRIJID , a hardware/software approach, where special instructions are used in the code for triggering the injection at runtime; and (2) autoRIJID , a hardware approach, where the code injection is triggered by the processor itself via detecting signatures of encryption routines at runtime. A novel signature detection technique is also introduced for identifying encryption routines within application programs at runtime. Further, a simple obfuscation metric ( RIJIDindex ) based on cross-correlation that measures the scrambling provided by any code injection technique is introduced, which coarsely indicates the level of scrambling achieved. Our processor models cost 1.9% additional area in the hardware/software approach and 1.2% in the hardware approach for a RISC based processor, and costs on average 29.8% in runtime and 27.1% in energy for the former and 25.0% in runtime and 28.5% in energy for the later, for industry standard cryptographic applications.

Tunable, mixed-resolution modeling using library-based Monte Carlo and graphics processing units.

Building on our recently introduced library-based Monte Carlo (LBMC) approach, we describe a flexible protocol for mixed coarse-grained (CG)/all-atom (AA) simulation of proteins and ligands. In the present implementation of LBMC, protein side chain configurations are pre-calculated and stored in libraries, while bonded interactions along the backbone are treated explicitly. Because the AA side chain coordinates are maintained at minimal run-time cost, arbitrary sites and interaction terms can be turned on to create mixed-resolution models. For example, an AA region of interest such as a binding site can be coupled to a CG model for the rest of the protein. We have additionally developed a hybrid implementation of the generalized Born/surface area (GBSA) implicit solvent model suitable for mixed-resolution models, which in turn was ported to a graphics processing unit (GPU) for faster calculation. The new software was applied to study two systems: (i) the behavior of spin labels on the B1 domain of protein G (GB1) and (ii) docking of randomly initialized estradiol configurations to the ligand binding domain of the estrogen receptor (ERα). The performance of the GPU version of the code was also benchmarked in a number of additional systems.

Logical inference techniques for loop parallelization

This paper presents a fully automatic approach to loop parallelization that integrates the use of static and run-time analysis and thus overcomes many known difficulties such as nonlinear and indirect array indexing and complex control flow. Our hybrid analysis framework validates the parallelization transformation by verifying the independence of the loop's memory references. To this end it represents array references using the USR (uniform set representation) language and expresses the independence condition as an equation, S =0, where S is a set expression representing array indexes. Using a language instead of an array-abstraction representation for S results in a smaller number of conservative approximations but exhibits a potentially-high runtime cost. To alleviate this cost we introduce a language translation F from the USR set-expression language to an equally rich language of predicates ( F ( S ) ==&gt; S = 0). Loop parallelization is then validated using a novel logic inference algorithm that factorizes the obtained complex predicates (F( S )) into a sequence of sufficient independence conditions that are evaluated first statically and, when needed, dynamically, in increasing order of their estimated complexities. We evaluate our automated solution on 26 benchmarks from PERFECT-Club and SPEC suites and show that our approach is effective in parallelizing large, complex loops and obtains much better full program speedups than the Intel and IBM Fortran compilers.

Postscheduling buffer management trade-offs in streaming software synthesis

Streaming applications, which are abundant in many disciplines such as multimedia, networking, and signal processing, require efficient processing of a seemingly infinite sequence of input data. In the context of streaming software synthesis from data flow graphs, we study the inherent trade-off between memory requirement and compilation runtime, under a given task firing schedule. We utilize postscheduling analysis granularity to control the amount of details in characterization of buffer's spatio-temporal footprints. Subsequently, we transform the buffer allocation problem to two-dimensional packing of polygons, where complexity of the packing problem (e.g., polygon shapes) is determined by the analysis granularity. We develop an evolutionary packing optimization algorithm which readily yields buffer allocations. Experimental results highlight the trade-off between complexity of the analysis and the total buffer size of generated implementations. In addition, they show dramatic improvements in total buffer size, if one is willing to pay the additional cost in optimization runtime.

Iteration and optimization scheme for the reconstruction of 3D surfaces based on non-uniform rational B-splines

Curve or surface reconstruction is a challenging problem in the fields of engineering design, virtual reality, film making and data visualization. Non-uniform rational B-spline (NURBS) fitting has been applied to curve and surface reconstruction for many years because it is a flexible method and can be used to build many complex mathematical models, unlike certain other methods. To apply NURBS fitting, there are two major difficult sub-problems that must be solved: (1) the determination of a knot vector and (2) the computation of weights and the parameterization of data points. These two problems are quite challenging and determine the effectiveness of the overall NURBS fit. In this study, we propose a new method, which is a combination of a hybrid optimization algorithm and an iterative scheme (with the acronym HOAAI), to address these difficulties. The novelties of our proposed method are the following: (1) it introduces a projected optimization algorithm for optimizing the weights and the parameterization of the data points, (2) it provides an iterative scheme to determine the knot vectors, which is based on the calculated point parameterization, and (3) it proposes the boundary-determined parameterization and the partition-based parameterization for unorganized points. We conduct numerical experiments to measure the performance of the proposed HOAAI with six test problems, including a complicated curve, twisted and singular surfaces, unorganized data points and, most importantly, real measured data points from the Mashan Pumped Storage Power Station in China. The simulation results show that the proposed HOAAI is very fast, effective and robust against noise. Furthermore, a comparison with other approaches indicates that the HOAAI is competitive in terms of both accuracy and runtime costs.

Efficient processing of top-k queries: selective NRA algorithms

Efficient processing of top-k queries has drawn increasing attention from both industry and academia due to its varied applications. Lower access cost is a crucial concern for a top-k query processing. Typically, when answering a top-k query, there exist two types of accesses: sorted access and random access. In some scenarios, the latter is not supported by the data source. Fagin et al. proposed the No Random Access (NRA) algorithm (Fagin et al, J Comput Syst Sci 66:614–656, 2003) for this situation. In this paper, we motivate our work by a key observation of the NRA algorithm: the number of accesses could be further reduced by selectively (instead of in parallel) performing sorted accesses to different lists of the dataset. Based on this insight, we propose a Selective NRA (SNRA) algorithm aiming to cut down the unnecessary access cost. Later, we optimize the SNRA algorithm in terms of runtime cost and present the SNRA-opt algorithm. Furthermore, we address the problem of instance optimality theoretically and turn SNRA (and SNRA-opt) into instance optimal algorithms, termed as Hybrid-SNRA (HSNRA) and HSNRA-opt. Extensive experimental results show that our algorithms perform significantly fewer sorted accesses than NRA (and its state-of-the-art variations). In terms of runtime cost, the proposed SNRA-opt and HSNRA-opt algorithms are two orders of magnitude faster than the NRA algorithm. In addition, we discuss the parameter selection problem of the SNRA algorithms, both theoretically and experimentally.

Clustering large attributed information networks: an efficient incremental computing approach

In recent years, many information networks have become available for analysis, including social networks, road networks, sensor networks, biological networks, etc. Graph clustering has shown its effectiveness in analyzing and visualizing large networks. The goal of graph clustering is to partition vertices in a large graph into clusters based on various criteria such as vertex connectivity or neighborhood similarity. Many existing graph clustering methods mainly focus on the topological structures, but largely ignore the vertex properties which are often heterogeneous. Recently, a new graph clustering algorithm, SA-cluster, has been proposed which combines structural and attribute similarities through a unified distance measure. SA-Cluster performs matrix multiplication to calculate the random walk distances between graph vertices. As part of the clustering refinement, the graph edge weights are iteratively adjusted to balance the relative importance between structural and attribute similarities. As a consequence, matrix multiplication is repeated in each iteration of the clustering process to recalculate the random walk distances which are affected by the edge weight update. In order to improve the efficiency and scalability of SA-cluster, in this paper, we propose an efficient algorithm In-Cluster to incrementally update the random walk distances given the edge weight increments. Complexity analysis is provided to estimate how much runtime cost Inc-Cluster can save. We further design parallel matrix computation techniques on a multicore architecture. Experimental results demonstrate that Inc-Cluster achieves significant speedup over SA-Cluster on large graphs, while achieving exactly the same clustering quality in terms of intra-cluster structural cohesiveness and attribute value homogeneity.

A Declarative Language Approach to Device Configuration

C remains the language of choice for hardware programming (device drivers, bus configuration, etc.): it is fast, allows low-level access, and is trusted by OS developers. However, the algorithms required to configure and reconfigure hardware devices and interconnects are becoming more complex and diverse, with the added burden of legacy support, “quirks,” and hardware bugs to work around. Even programming PCI bridges in a modern PC is a surprisingly complex problem, and is getting worse as new functionality such as hotplug appears. Existing approaches use relatively simple algorithms, hard-coded in C and closely coupled with low-level register access code, generally leading to suboptimal configurations. We investigate the merits and drawbacks of a new approach: separating hardware configuration logic (algorithms to determine configuration parameter values) from mechanism (programming device registers). The latter we keep in C, and the former we encode in a declarative programming language with constraint-satisfaction extensions. As a test case, we have implemented full PCI configuration, resource allocation, and interrupt assignment in the Barrelfish research operating system, using a concise expression of efficient algorithms in constraint logic programming. We show that the approach is tractable, and can successfully configure a wide range of PCs with competitive runtime cost. Moreover, it requires about half the code of the C-based approach in Linux while offering considerably more functionality. Additionally it easily accommodates adaptations such as hotplug, fixed regions, and “quirks.”