Run-time Reconfiguration Research Articles

Dynamic IoT deployment reconfiguration: A global-level self-organisation approach

The edge-cloud continuum provides a heterogeneous, multi-scale, and dynamic infrastructure supporting complex deployment profiles and trade-offs for application scenarios like those found in the Internet of Things and large-scale cyber–physical systems domains. To exploit the continuum, applications should be designed in a way that promotes flexibility and reconfigurability, and proper management (sub-)systems should take care of reconfiguring them in response to changes in the environment or non-functional requirements. Approaches may leverage optimisation-based or heuristic-based policies, and decision making may be centralised or distributed: this work investigates decentralised heuristic-based approaches. In particular, we focus on the pulverisation approach, whereby a distributed software system is automatically partitioned (“pulverised”) into different deployment units. In this context, we address two main research problems: how to support the runtime reconfiguration of pulverised systems, and how to specify decentralised reconfiguring policies by a global perspective. To address the first problem, we design and implement a middleware for pulverised systems separating infrastructural and application concerns. To address the second problem, we leverage aggregate computing and exploit self-organisation patterns to devise self-stabilising reconfiguration strategies. By simulating deployments on different kinds of complex infrastructures, we assess the flexibility of the pulverisation middleware design as well as the effectiveness and resilience of the aggregate computing-based reconfiguration policies.

NC-Library: Expanding SystemC Capabilities for Nested reConfigurable Hardware Modelling

As runtime reconfiguration is used in an increasing number of hardware architectures, new simulation and modeling tools are needed to support the developer during the design phases. In this article, a language extension for SystemC is presented, together with a design methodology for the description and simulation of dynamically reconfigurable hardware at different levels of abstraction. The library presented offers a high degree of flexibility in the description of reconfiguration features and their management, while allowing runtime reconfiguration simulation, removal, and replacement of custom modules as well as third-party components throughout the architecture development process. In addition, our approach supports the emerging concept of nested reconfiguration and split regions with a minimal simulation overhead of a maximum of three delta cycles for signal and transaction forwarding, and four delta cycles for the reconfiguration process.

FPGA approximate logic synthesis through catalog-based AIG-rewriting technique

Due to their run-time reconfigurability, short time-to-market, and lower prototype costs, FPGAs have become increasingly popular since their introduction. They found use in a wide variety of applications, including high-performance computing. However, when compared to ASICs, FPGAs offer lower performance, and they are power-hungry devices with low energy-efficiency. The emergence of Approximate Computing (AxC) represents a significant advancement in terms of enabling technology when applied to FPGA-based computing platforms. It has been effectively exploited in several application fields, achieving significant savings in energy and latency through a selective degradation of the output quality. Nevertheless, a generalized and systematic methodology for FPGA-based circuit design is still lacking. Indeed, most of the methods target ASIC-based systems, and, consequently, they offer minimal advantages or even an increase in resources when synthesized for FPGAs due to the architectural differences between the technologies.In this paper, we attempt to address this shortcoming by introducing our method for designing combinational logic circuits. It is based on and-inverter graph rewriting and multi-objective optimization, aiming for optimal trade-offs between quality of results and hardware overhead. Extensive experimental campaigns empirically prove that both generic logic and arithmetic circuits benefit from this approach.

Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-Based Accelerators

Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-Based Accelerators

Modeling variability in self-adapting robotic systems

Autonomous robots operating in everyday environments, such as hospitals, private houses, and public roads, are context-aware self-adaptive systems, i.e. they exploit knowledge about their resources and the environment to trigger runtime adaptation, so that they exhibit a behavior adequate to the current context. For these systems, context-aware self-adaptation requires to design the robot control application as a dynamically reconfigurable software architecture and to specify the adaptation logic for reconfiguring its variable aspects (e.g. the modules that implement various obstacle detection algorithms or control different distance sensors) according to specific criteria (e.g. enhancing robustness against variable illumination conditions). Despite self-adaptation is an intrinsic capability of autonomous robots, ad-hoc approaches are used in practice to design reconfigurable robot architectures. In order to enhance system maintainability, the control logic and the adaptation logic should be loosely coupled. For this purpose, the adaptation logic should be defined against an explicit representation of software variability in the robot control architecture. In this paper we propose a modeling approach, which consists in explicitly representing robot software variability with the MARTE::ARM-Variability metamodel, which has been designed as an extension of the UML MARTE profile. We evaluate the applicability of the proposed approach by exemplifying the software architecture design of a robot navigation framework and by analyzing the support provided by the ROS infrastructure for runtime reconfiguration of its variable aspects.

MORPHEMIC - Optimization of the Deployment and Life-cycle Management of Data-intensive Applications in the Cloud Computing Continuum

In their Cloud strategy companies are choosing more and more multi-cloud computing giving them the opportunity to distribute its assets, redundancies, software, applications, and anything it deems worthy not only on one Cloud-hosting environment, but rather across several. The model of using multiple Cloud services to host the business's functions and features has a list of advantages that can provide security, flexibility, cost-effectiveness and more to increase business's efficiency and ensure it stays up and running 24 hours a day. The paper presents the MORPHEMIC H2020 project and its unique way of adapting and optimising Cloud computing applications. The Morphemic project covers several features from modelling cross-cloud applications, continuous and autonomous optimization and deployment and providing access to several cloud capabilities for data intensive applications. The outcome of the project will be implemented in the form of an open-source platform covering all the data intensive applications deployment phases starting from modelling, through profiling, optimization, runtime reconfiguration and monitoring.

A Domain-Specific Accelerator for Ultralow Latency Market Data Distribution System

Ultralow latency parsing of financial data is gaining significance in the high-frequency trading of the security exchange market. Hardware-aided systems exhibit superior improvement of latency over traditional software solutions, but flexibility may suffer when processing the financial protocol. This article presents a domain-specific accelerator for the market data distribution system, which integrates a financial information exchange adapted for streaming (FAST) decoder, a 10-Gbps network interface, and a high-speed PCIe host interface into a single field programmable gate array (FPGA) acceleration card. The proposed FAST decoder adopts the finite state machines-coordinated sequence mapping table to achieve run-time reconfigurability over fine-grained FPGA programming, and 16 fields can be decoded simultaneously in a pipelined manner, resulting in a decoding latency of only 33 ns. Evaluated on the Xilinx Alveo U200 acceleration card, this work improves the latency of decoding a FAST message by 26%–72% than state-of-the-art FPGA designs, and outperforms the software baseline by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$&gt;27\times$</tex-math></inline-formula> in terms of latency covering both decoding and communication.

Skyrmion based 3D low complex runtime reconfigurable architecture design methodology of universal logic gate

In this study, we introduce the area efficient low complex runtime reconfigurable architecture design methodology based on Skyrmion logic for universal logic gate (ULG) i.e. NOR/NAND implementation using micromagnetic simulations. We have modelled the two input 3D device structure using bilayer ferromagnet/heavy metal where the magnetic tunnel junctions inject and detect the input and output skyrmions by exploiting the input reversal mechanism. The implementation of NOR and NAND is performed using this same device where it is reconfigured runtime with enhanced tunability by the ON and OFF state of current passing through a non magnetic metallic gate respectively. This gate acts as a barrier for skyrmion motion (additional control mechanism) to realize the required Skyrmion logic output states. To the best of authors’s knowledge the boolean optimizations and the mapping logic have been presented for the first time to demonstrate the functionalities of the NOR/NAND implementation. This proposed architecture design methodology of ULG leads to reduced device footprint with regard to the number of thin film structures proposed, low complexity in terms of fabrication and also providing runtime reconfigurability to reduce the number of physical designs to achieve all truth table entries (∼75% device footprint reduction). The proposed 3D ULG architecture design benefits from the miniaturization resulting in opening up a new perspective for magneto-logic devices.

Runtime reconfiguration of data services for dealing with out-of-range stream fluctuation in cloud-edge environments

The integration of cloud and IoT edge devices is of significance in reducing the latency of IoT stream data processing by moving services closer to the edge-end. In this connection, a key issue is to determine when and where services should be deployed. Common service deployment strategies used to be static based on the rules defined at the design time. However, dynamically changing IoT environments bring about unexpected situations such as out-of-range stream fluctuation, where the static service deployment solutions are not efficient. In this paper, we propose a dynamic service deployment mechanism based on the prediction of upcoming stream data. To effectively predict upcoming workloads, we combine the online machine learning methods with an online optimization algorithm for service deployment. A simulation-based evaluation demonstrates that, compared with those state-of-the art approaches, the approach proposed in this paper has a lower latency of stream processing.

Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAs

Nowadays, field programmable gate arrays (FPGAs) have been widely adopted to serve as accelerators in artificial intelligence and big data related applications. Since the static random access memory (SRAM)-based FPGA is suffering from limited density and high leakage power, nonvolatile FPGAs have been proposed, where SRAM is replaced with emerging nonvolatile memories (NVMs). Multilevel cell (MLC), which can store multiple bits within one memory cell, further improves the density of nonvolatile FPGAs and shows great potential to enable large on-chip memory. However, it suffers from limited lifetime. In this article, we propose a wear leveling scheme to improve lifetime of MLC-based nonvolatile FPGAs. Instead of generating a series of configuration files for runtime reconfiguration, we propose to identify write-heavy MLC regions and dynamically transform them to durable single-level cell (SLC) mode. Specifically, we propose three modules: 1) pertaining to write behavior monitor; 2) approximate cost calculator; and 3) mode transformation manager to achieve adaptive mode transformations. We consider FPGA features to design these modules, which is different from implementations for MLC-SLC transformation in CPU architecture. Evaluation shows that the proposed scheme can improve lifetime for MLC nonvolatile FPGAs by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.03\times $ </tex-math></inline-formula> , at cost of 12.5% storage overhead.

Fries

A computing job in a big data system can take a long time to run, especially for pipelined executions on data streams. Developers often need to change the computing logic of the job such as fixing a loophole in an operator or changing the machine learning model in an operator with a cheaper model to handle a sudden increase of the data-ingestion rate. Recently many systems have started supporting runtime reconfigurations to allow this type of change on the fly without killing and restarting the execution. While the delay in reconfiguration is critical to performance, existing systems use epochs to do runtime reconfigurations, which can cause a long delay. In this paper we develop a new technique called Fries that leverages the emerging availability of fast control messages in many systems, since these messages can be sent without being blocked by data messages. We formally define consistency in runtime reconfigurations, and develop a Fries scheduler with consistency guarantees. The technique not only works for different classes of dataflows, but also works for parallel executions and supports fault tolerance. Our extensive experimental evaluation on clusters show the advantages of this technique compared to epoch-based schedulers.

Reconfigurable Smart Contracts for Renewable Energy Exchange with Re-Use of Verification Rules

Smart contracts constitute the foundation for blockchain distributed applications. These constructs enable transactions in trustless environments using consensus algorithms and software-controlled verification rules. In the current state of the art, there is a shortage of works on the adaptability of smart contracts, and the re-use of their source code is limited mainly to cloning. The paper discusses the pattern of smart contract design and implementation with the overt declaration of verification rules. The author introduces two advantages of the pattern: Firstly, run-time reconfigurability of the list of smart contract verification rules to adjust for various transaction types. Secondly, the re-use of verification rules between different configurations of the smart contract, and among diverse smart contracts. The paper uses blockchain platform-independent stereotypes from a dedicated Unified Modeling Language (UML) profile for designing smart contracts and verification rules. The implementation of the pattern is developed in object-oriented Java language. The pattern exploits polymorphism and controls inheritance by using sealed classes with permission for specialization only for selected final ones. Thus, the pattern ensures two recently highly desired properties in smart contract design and development: re-use and security. Moreover, the declared verification rules list facilitates test automation and reduces test preparation effort due to the re-use of test classes among smart contract configurations. The pattern usage is illustrated in the example of renewable energy exchange within the prosumers community and amid various communities.

Run-Time Reconfiguration Strategy and Implementation of Time-Triggered Networks

Time-triggered networks are deployed in avionics and astronautics because they provide deterministic and low-latency communications. Remapping of partitions and the applications that reside in them that are executing on the failed core and the resulting re-routing and re-scheduling are conducted when a permanent end-system core failure occurs and local resources are insufficient. We present a network-wide reconfiguration strategy as well as an implementation scheme, and propose an Integer Linear Programming based joint mapping, routing, and scheduling reconfiguration method (JILP) for global reconfiguration. Based on scheduling compatibility, a novel heuristic algorithm (SCA) for mapping and routing is proposed to reduce the reconfiguration time. Experimentally, JILP achieved a higher success rate compared to mapping-then-routing-and-scheduling algorithms. In addition, relative to JILP, SCA/ILP was 50-fold faster and with a minimal impact on reconfiguration success rate. SCA achieved a higher reconfiguration success rate compared to shortest path routing and load-balanced routing. In addition, scheduling compatibility plays a guiding role in ILP-based optimization objectives and ‘reconfigurable depth’, which is a metric proposed in this paper for the determination of the reconfiguration potential of a TT network.

A Run-Time Reconfiguration Method for an FPGA-Based Electrical Capacitance Tomography System

A desirable feature of an electrical capacitance tomography system is the adaptation possibility to any sensor configuration and measurement mode. A run-time reconfiguration of a system for electrical capacitance tomography is presented. An original mechanism is elaborated to reconfigure, on the fly, a modular EVT4 system with multiple FPGAs installed. The outlined system architecture is based on FPGA programmable logic devices (Xilinx Spartan) and PicoBlaze soft-core processors. Soft-core processors are used for communication, measurement control and data preprocessing. A novel method of FPGA partial reconfiguration is described, in which a PicoBlaze soft-core processor is used as a reconfiguration controller. Behavioral reconfiguration of the system is obtained by providing run-time access to the program code of a soft-core control processor. The tests using EVT4 hardware and different algorithms for tomographic scanning were performed. A test object was measured using 2D and 3D sensors. The time and resources required for the examined reconfiguration procedure are evaluated.

RuVa: A Runtime Software Variability Algorithm

Context-aware and smart systems that require runtime reconfiguration to cope with changes in the environment increasingly demand variability management mechanisms that can address runtime concerns. In recent years, we have witnessed new dynamic variability solutions using dynamic software product line (DSPL) approaches. However, while few solutions proposed so far have addressed the need to add, change and remove variants dynamically, none of them provide a way to check the constraints between features at runtime. Because all SAT solvers perform variability constraint checking in off-line mode, we suggest in this ongoing research paper the integration of RuVa, a runtime variability algorithm, with the FaMa tool suite to check feature constraints dynamically before a new feature is added or an existing feature is removed. This research suggests a novel approach to modifying the variability model of context-aware systems dynamically and check the feature constraints on the fly.We integrate our solution with a SAT solver that can be invoked at runtime by a cyber-physical system.We validate the effectiveness and performance of the proposed algorithm using simulations.We also provide a proof-of-concept for updating the configuration of a robot’s variability model based on contextual changes.

A Runtime Reconfigurable Design of Compute-in-Memory–Based Hardware Accelerator for Deep Learning Inference

Compute-in-memory (CIM) is an attractive solution to address the “memory wall” challenges for the extensive computation in deep learning hardware accelerators. For custom ASIC design, a specific chip instance is restricted to a specific network during runtime. However, the development cycle of the hardware is normally far behind the emergence of new algorithms. Although some of the reported CIM-based architectures can adapt to different deep neural network (DNN) models, few details about the dataflow or control were disclosed to enable such an assumption. Instruction set architecture (ISA) could support high flexibility, but its complexity would be an obstacle to efficiency. In this article, a runtime reconfigurable design methodology of CIM-based accelerators is proposed to support a class of convolutional neural networks running on one prefabricated chip instance with ASIC-like efficiency. First, several design aspects are investigated: (1) the reconfigurable weight mapping method; (2) the input side of data transmission, mainly about the weight reloading; and (3) the output side of data processing, mainly about the reconfigurable accumulation. Then, a system-level performance benchmark is performed for the inference of different DNN models, such as VGG-8 on a CIFAR-10 dataset and AlexNet GoogLeNet, ResNet-18, and DenseNet-121 on an ImageNet dataset to measure the trade-offs between runtime reconfigurability, chip area, memory utilization, throughput, and energy efficiency.

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.

A FPGA-based end-to-end acceleration framework for fast deployment of Convolutional Neural Networks

Nowadays, CNNs has delivered the state-of-the-art performance in the field of computer vision, image classification, etc. As CNNs going deeper, it becomes more difficult to implement CNNs applications based on general-purpose computing platforms. Recently, many FPGA-based CNNs accelerators have been proposed, these accelerators achieved high performance on specific CNNs models, however they are somewhat lack of reconfigurability to fit different applications. To deal with this problem, an end-to-end acceleration framework was proposed in this paper, which consists of a parameterized hardware accelerator and a fully automatic software framework. Parallel computation and pipeline optimization are deployed in the hardware design to achieve high performance. Simultaneously, runtime reconfigurability is implemented by using a global register list. By encapsulating the underlying driver, a three-layer software framework is provided for users to deploy their pre-trained models. A typical CNNs model used for handwritten digital recognition was selected to test and verify the accelerator. The experimental result shows that the accelerator can reach a recognition speed of 22.65FPS under the clock frequency of 100MHz, comparing with ARM Cortex-A9 working at 650MHz, it can achieve 25.9 times of acceleration effect, with only 1.59W power consumption.

An analysis of power consumption and performance in runtime hardware reconfiguration

It will be more difficult to continue with Moore's law scaling in the next years without exploring new heterogeneous architectures with application-customised hardware. The expressive employment of customised accelerators, or runtime reconfigurable designs, will be required to deliver power- and performance-efficient systems. In view of recent technology advances, runtime partial reconfiguration has emerged supported by FPGA-based devices. Still, power consumption and performance are the principal concerns when devising new reconfigurable embedded systems. This paper addresses power and performance analysis of the partial reconfiguration process supported by runtime reconfigurable hardware. We introduce a heterogeneous system-on-chip FPGA-based runtime partial reconfigurable platform design along with an experimental and theoretical power consumption and performance models, which are specific to the partial reconfiguration process. The proposed design was implemented, and both experimental and theoretical power consumption and performance analyses were performed, thus providing a formal tool to the decision-making process between power consumption and performance applicable to the runtime reconfiguration phase. Results show an average accuracy of 89.76% for the power consumption model and 94.82% for the performance model.

Classification and Mapping of Model Elements for Designing Runtime Reconfigurable Systems

Classification and Mapping of Model Elements for Designing Runtime Reconfigurable Systems