An analysis of power consumption and performance in runtime hardware reconfiguration

Abstract

It will be more difficult to continue with Moore's law scaling in the next years without exploring new heterogeneous architectures with application-customised hardware. The expressive employment of customised accelerators, or runtime reconfigurable designs, will be required to deliver power- and performance-efficient systems. In view of recent technology advances, runtime partial reconfiguration has emerged supported by FPGA-based devices. Still, power consumption and performance are the principal concerns when devising new reconfigurable embedded systems. This paper addresses power and performance analysis of the partial reconfiguration process supported by runtime reconfigurable hardware. We introduce a heterogeneous system-on-chip FPGA-based runtime partial reconfigurable platform design along with an experimental and theoretical power consumption and performance models, which are specific to the partial reconfiguration process. The proposed design was implemented, and both experimental and theoretical power consumption and performance analyses were performed, thus providing a formal tool to the decision-making process between power consumption and performance applicable to the runtime reconfiguration phase. Results show an average accuracy of 89.76% for the power consumption model and 94.82% for the performance model.