Gate Array Routing Research Articles

Effective Drive Current for Pass-Gate Transistors

A two-point expression of effective drive current ( $I_{\rm eff\_{}PG})$ for pass-gate (PG) transistors is proposed for the first time. We demonstrate that the proposed expression of $I_{\rm eff\_{}PG}$ estimates the PG latency with a reasonable accuracy (relative error $I_{\rm eff\_{}PG}$ provides a simple yet efficient approach for technology evaluation and projection for PG heavy applications such as field-programmable gate array routing. We also show that the previously proposed static CMOS effective drive current ( $I_{\rm eff\_{}inv})$ is not a valid figure of merit when applied to PG transistors, because PG transistors operate in a different regime from the transistors in CMOS inverters. The scaling trend of $I_{\rm eff\_{}PG}$ is discussed, which illustrates the $I_{\rm eff\_{}PG}$ does not improve from device scaling as much as CMOS saturation current ( $I_{{\mathrm{dsat}}})$ and effective drive current ( $I_{\rm eff\_{}inv})$ do.

The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources

As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications. Large arithmetic intensive applications often contain a large proportion of datapath circuits. Since datapath circuits are designed to process multiple-bit-wide data, FPGAs implementing these circuits often have to transport a large amount of multiple-bit-wide signals from one computing element (such as a logic block, a DSP block, or a multi-bit addressable memory cell) to another. In this work, we investigate the area efficiency of FPGA routing resources for transporting multiple-bit-wide signals. It is shown that, for datapath circuits, the switch patterns used by the conventional routing architecture, which uniformly distribute routing switches across the routing tracks, are inefficient for connecting the computing elements to their tracks. The more efficient multi-bit aware patterns, which contain a densely populated single-bit region and a sparsely populated multi-bit region, can be effectively used to reduce the routing area of FPGAs for implementing arithmetic intensive applications by 6%-10%. It is also shown that the further sharing of configuration memory among the switches within the multi-bit aware patterns does not significantly increase their area efficiency since datapath circuits typically contain a mixture of multi-bit and single-bit signals-while configuration memory sharing can substantially increase the area efficiency of routing resources for transporting multi-bit signals, it also significantly reduces their ability for transporting single-bit signals. More importantly, configuration memory sharing can significantly reduce the effectiveness of the enhanced multi-bit aware patterns-patterns that incorporate both multi-bit aware and single-bit oriented switches within a single region in order to increase its ability for transporting both single-bit and multi-bit signals.

Sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing

Advances in methods for solving Boolean satisfiability (SAT) for large problems have motivated recent attempts to recast physical design problems as Boolean SAT problems. One persistent criticism of these approaches is their inability to supply partial solutions, i.e., to satisfy most but not all of the constraints cast in the SAT style. In this paper, we present a formulation for "subset satisfiable" Boolean SAT: we transform a "strict" SAT problem with N constraints into a new, "relaxed" SAT problem which is satisfiable just if not more than k/spl Lt/N of these constraints cannot be satisfied in the original problem. We describe a transformation based on explicit thresholding and counting for the necessary SAT relaxation. Examples from field-programmable gate-array routing show how we can determine efficiently when we can satisfy "almost all" of our geometric constraints.

Guest editorial: System-level interconnect prediction

for hierarchically placed cells. The new approach splits nets into two-terminal segments and develops a technique based on a generating polynomial representation of the segment lengths to correctly calculate the Steiner length of the reconstructed net. The generating polynomial representation allows all possible net segment length combinations to be computed in an efficient manner and results in a net length averaged over all equally likely routing alternatives. The final two contributions to the special section are on the application of SLIP techniques to the optimal design and layout of programmable logic devices. The paper by Rahman et al. addresses methods for the design of an SRAM-based programmable gate array routing architecture. It proposes an optimal design in which the range of predefined wire lengths approximates the wire length distribution estimate of a representative netlist. The problem is thus transformed into a Rentian wire length estimation problem. Since it is based on an analytical model, the extension of the analysis to the design of three-dimensional (3-D) architectures with 3-D routing switches is also considered. The final brief by Hutton

Clock distribution networks in synchronous digital integrated circuits

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed.

General gate array routing using a k-terminal net routing algorithm with failure prediction

A general approach to gate array routing based on an abstract routing space model is presented. An efficient k-terminal net maze runner is described. It does not partition nets into two-terminal net routing problems, but solves the problem by simultaneously growing k search waves. It is shown that the explored routing space diminishes when compared to bidirectional routing schemes. Experimental data show a reduction of CPU time up to 55% and a decrease of total net length up to 6% compared to a bidirectional maze router. For k-terminal nets it is shown that net length decreases with increasing k. Additional routing space restriction is attained by use of variable search space restriction and by the introduction of a dynamic routing space partitioning method based on the concept of regions. This concept allows for determination of nonroutable nets or parts of nets in an efficient way. The new partitioning method may be implemented in any maze runner without increasing the complexity of the maze runner algorithm. Results show an additional decrease of CPU time up to 35%. >

A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays

The channel router, which routes a rectangular channel with two rows of terminals along its top and bottom sides, is extensively used for the automatic routing of gate arrays. It is well known that in this routing method the routing can not be performed when the vertical constraint graph contains cycles. This paper deals with the problem of eliminating cycles in the vertical constraint graph by interchanging the nets assigned to logically equivalent terminals before channel routing. A heuristic algorithm is proposed for this problem. This algorithm yields a locally optimum assignment of nets to terminals, in the sense that the number of independent cycles in the vertical constraint graph of a resultant assignment can not be reduced by interchanging any pair of the nets assigned to logically equivalent terminals. Furthermore, in order to speed up the operation of this algorithm, it is shown that the checking as to whether or not the number of independent cycles in the vertical constraint graph is reduced can be done by noting only its subgraph, when a pair of nets assigned to logically equivalent terminals are interchanged. Experimental results have indicated that this proposed algorithm is efficient.

Global Routing for Gate Array

We propose a new approach to the global routing of gate arrays. The method can handle any channel capacities and pin distributions on the chip. The global router first finds unique routes, then pushes connections to the periphery. As outer wiring capacity is consumed, the routing continues inward, connecting pins and making global cell assignments for nets by a centrifugal layering process. The goal is to avoid congestion in the center of the chip, a common problem with conventional methods.

Hierarchical Wire Routing

We propose a new approach to automatic wire routing of VLSI chips which is applicable to interconnection problem in uniform structures such as gate arrays, switchboxes, channels. Popularity of gate arrays technologies still remains high among VLSI chip manufacturers and, as the scale of integration grows, the interconnection problem becomes increasingly difficult if not intractable. The same is true for problems of switchbox and channel routing, which usually arise in custom designs; the uniformity of wiring substrate unites them with gate array routing problem. Our approach was initially aimed at gate arrays, but it extends naturally to switchboxes and channels. Uniformity of the wiring substrate is the crucial assumption of the method. It assumes that horizontal and vertical wire segments are realized on different wiring layers and vias are introduced each time a wire changes direction. Any "jogs" ("wrong way" wires) are prohibited. Within these limitations our approach is advantageous over the existing wiring methodologies. Our final layout of wires is independent of both net ordering and ordering of pins within the nets. The wire densities we are able to achieve are often higher than those achieved by other routers. Because of the hierarchical nature of our method it is inherently fast, usually by an order of magnitude faster than the routers based on wave propagation (maze running) technique.