Global Routing for Gate Array

Abstract

We propose a new approach to the global routing of gate arrays. The method can handle any channel capacities and pin distributions on the chip. The global router first finds unique routes, then pushes connections to the periphery. As outer wiring capacity is consumed, the routing continues inward, connecting pins and making global cell assignments for nets by a centrifugal layering process. The goal is to avoid congestion in the center of the chip, a common problem with conventional methods.