Routing Architecture Research Articles

Knowledge Graph Aided Network Representation and Routing Algorithm for LEO Satellite Networks

The compelling applications of Low earth orbit (LEO) satellite networks in our daily lives have been witnessed in recent years, ranging from weather forecasts to military monitoring. LEO satellite networks have grown in importance as a complement to terrestrial networks aiming at delivering global, ubiquitous communication. However, due to the LEO network topology keeps changing dynamically, the development of efficient routing algorithms becomes one of the challenges in the LEO network. Traditional routing policies hardly solve the rerouting problem caused by link switchover and the high calculation cost caused by large-scale irregular satellite topology. In this paper, we propose a knowledge graph-aided representation of satellite network topologies and routing architecture to optimize path selection and calculation cost for lower packet loss ratio and average delay. Moreover, we generate a routing policy by predicting potential relations between data packets and nodes to select the best relay nodes with the maximum probability of forwarding relations. Finally, extensive simulations are performed to evaluate the performance and availability of our proposed algorithm.

Proficient matrix codes for error detection and correctionin 8-port network on chip routers

This paper verifies the applicability of the proposed code to dynamic Network on Chips that have variable faulty blocks with runtime suggesting an online error detection mechanism with adaptive routing algorithm that bypasses faulty components dynamically and the router architecture uses additional diagonal state indications for the reliable network on chip (NoC) operation. In NoC, the permanently faulty routers are disconnected to enable high runtime throughput as data packets are not lost due to self-loopback mechanism. The proposed proficient matrix codes use the capabilities of decimal matrix code technique with minimum check bits for maximum error correction capability. The proposed code is compared with existing codes such as decimal matrix codes, modified decimal matrix codes and parity matrix codes. The codes are developed in verilog hardware description language and simulated in the Xilinx ISE 14.5 tool. This proficient matrix code proves to be efficient for multiple adjacent error detection and correction with trade off in delay. Also 65% code rate is achieved with 22.73% less redundant bits that occupy less area by atleast 11.78%. The codes when used for increased data sizes like 8, 16, 32, and 64 bits, the power delay product decreased by atleast 1.74%.

Micro SIDs: A Solution for Efficient Representation of Segment IDs in SRv6 Networks

The Segment Routing (SR) architecture is based on source routing. Within an SR enabled network, a list of instructions called segments can be added to the packet headers to influence the forwarding and the processing of the packets. In SRv6 (Segment Routing over IPv6 data plane) the segments are represented with IPv6 addresses, which are 16 bytes long. There are some SRv6 service scenarios that may require to carry a large number of segments in the IPv6 packet headers. Reducing the size of these overheads is useful to minimize the impact on MTU (Maximum Transfer Unit) and to enable SRv6 on legacy hardware devices with limited processing capabilities that could suffer from the long headers. In this paper we present the Micro SID solution for the efficient representation of segment identifiers. The proposed Micro SID solution has been implemented on three different architectures (VPP, Linux, P4) and interoperability tests have been performed. We also analyze the reduction of the header size that can be achieved with Micro SIDs and compare it with other proposals for segment list compression. Our results show that the header size can be reduced up to 75%. Finally, we mention that a fundamental asset of the proposed Micro SID solution is the full compatibility and seamless interoperability with existing SRv6 architecture.

Investigating on Black Holes in Segment Routing Networks: Identification and Detection

Network Black Holes (BHs) are logical failures that create a service disruption for a subset of traffic flows, generally due to device misconfiguration. Detection of a BH is a hard task due to its specific nature: the infrastructure is up and the disconnection affects a limited number of flows. An example of BH is the one caused by the failure of the Path MTU Discovery procedure in IPv6. The Segment Routing (SR) Architecture is an overlay infrastructure that provides source routing support by exploiting the connectivity service offered by the underlay IPv6 (SRv6). Thus, SR inherits the problems related to BHs affecting IPv6. In SR this problem is even more stressed due to the encapsulation mechanism that is required to enforce the segment lists on packets. Even worse, existing active probing based tools to detect network BHs for IPv6 are not suitable in SR. In this paper we investigate the problem of detecting SR Black Holes in SR domains. As first, we provide an experimental demonstration of the creation of an SR Black Holes. Then we show that existing tools based on active probing are not suitable to detect SR BHs. Then, a passive framework named Segment Routing Black Holes Detection (SR-BHD) is introduced. SR-BHD makes use of specific traffic counters available in SR capable nodes to verify the validity of the flow conservation principle on each network element. Experimental evaluation carried out through simulation and emulation shows the effectiveness of SR-BHD in detecting the presence of SR BHs.

Energy aware data harvesting strategy based on optimal node selection for extended network lifecycle in smart dust

Smart Dust environment face additional challenges as a result of the use of movable Smart Dust basestation(BS), despite its benefits. The main point of contention is the BS positioning updates to the smart dust nodes. Each smart object ought to be aware of the BS location so that it can send its data to the BS. According to the prevailing Flooding approach, the moveable BS must continuously distribute its location throughout the network in order to inform smart dust nodes about the BS location. In every case, visit positioning upgrades from the BS can result in maximal power usage as well as enhanced network breakdowns. Different sorts of routing architectures can be used to reduce BS position updating. A routing strategy based on the movable BS is successful if it preserves the network network’s power consumption and latencies to a minimum. The study’s main goal is to develop an energy-efficient routing mechanism focused on adaptive movable BS modification. In the Smart Dust Head (SDH) establishing the inferred surroundings, the most latest movable BS location will be preserved. As a result, rather than soliciting SDH in the environment, the location of the BS is propagated to the smart dust nodes located at the sectors in integrated networking. By transmitting request information to the nearest sector, the remaining SDH can find the most current BS location. The message’s recipient is determined based on the information gathered. The best fuzzy related clustering algorithm will be used to accomplish this. The Enhanced Oppositional grey wolf optimization (EOGWO) methodology can be used to perform the improvement. Optimum network throughput, low latency, and other metrics are used to assess performance. To enhance productivity, the findings will be analyzed and compared to previous routing methodologies.

A Blockchain-Based Deep-Learning-Driven Architecture for Quality Routing in Wireless Sensor Networks

Over the past few years, great importance has been given to wireless sensor networks (WSNs) as they play a significant role in facilitating the world with daily life services like healthcare, military, social products, etc. However, heterogeneous nature of WSNs makes them prone to various attacks, which results in low throughput, and high network delay and high energy consumption. In the WSNs, routing is performed using different routing protocols like low-energy adaptive clustering hierarchy (LEACH), heterogeneous gateway-based energy-aware multi-hop routing (HMGEAR), etc. In such protocols, some nodes in the network may perform malicious activities. Therefore, four deep learning (DL) techniques and a real-time message content validation (RMCV) scheme based on blockchain are used in the proposed network for the detection of malicious nodes (MNs). Moreover, to analyse the routing data in the WSN, DL models are trained on a state-of-the-art dataset generated from LEACH, known as WSN-DS 2016. The WSN contains three types of nodes: sensor nodes, cluster heads (CHs) and the base station (BS). The CHs after aggregating the data received from the sensor nodes, send it towards the BS. Furthermore, to overcome the single point of failure issue, a decentralized blockchain is deployed on CHs and BS. Additionally, MNs are removed from the network using RMCV and DL techniques. Moreover, legitimate nodes (LNs) are registered in the blockchain network using proof-of-authority consensus protocol. The protocol outperforms proof-of-work in terms of computational cost. Later, routing is performed between the LNs using different routing protocols and the results are compared with original LEACH and HMGEAR protocols. The results show that the accuracy of GRU is 97%, LSTM is 96%, CNN is 92% and ANN is 90%. Throughput, delay and the death of the first node are computed for LEACH, LEACH with DL, LEACH with RMCV, HMGEAR, HMGEAR with DL and HMGEAR with RMCV. Moreover, Oyente is used to perform the formal security analysis of the designed smart contract. The analysis shows that blockchain network is resilient against vulnerabilities.

Generative Boltzmann Adversarial Network in Manet Attack Detection and QOS Enhancement with Latency

Mobile Ad-Hoc Network (MANET) are considered as self-configured network those does not have any centralized base station for the network monitoring and control. MANET environment does not control architecture for routing for the frequent maintenance of topology. The drastic development of Internet leads to adverse effect of development in MANET for different multimedia application those are sensitive to latency. Upon the effective maintenance of the QoS routing route discovery is performed to calculate queue and contention delay. However, the MANET requirement comprises of the complex procedure to withstand the Quality of Service (QoS) with Artificial Intelligence (AI). In MANET it is necessary to compute the MANET attacks with improved QoS with the reduced latency as existing model leads to higher routing and increased latency. In this paper proposed a Generative Boltzmann Networking Weighted Graph (GBNWG) model for the QoS improvement in MANET to reduce latency. With GBNWG model the MANET model network performance are computed with the weighted graph model. The developed weighted graph computes the routes in the MANET network for the estimation of the available path in the routing metrices. The proposed GBNWG model is comparatively estimated with the conventional QOD technique. Simulation analysis stated that GBNWG scheme exhibits the improved performance in the QoS parameters. The GBNWG scheme improves the PDR value by 12%, 41% reduced control packets and 45% improved throughput value.

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Today, the current buffered router Synchronous Network on Chip architecture consumes significant chip area and power. Therefore, based on biased routing, buffer-less routers have recently been predicted as a possible solution, but they suffer from contiguous port assignments, slow critical paths, and increased latency. Asynchronous Network on Chip architecture emerges as the best option for avoiding glitches and consuming less power. A clock and data recovery circuit is used to recover the clock signal from the router-generated data and reduce power consumption in a Multiprocessor System on Chip. This paper proposes a clock and data recovery circuit design for an asynchronous Network on Chip. The proposed 4x4 Mesh router architecture implemented in this paper can process 64-bit of data samples with a depth of 64. When comparing the proposed architecture with the existing NoC architecture, the proposed architecture has shown a power reduction of 5times. The proposed architecture has consumed a total power of 0.103W.

An Optimized GIB Routing Architecture with Bent Wires for FPGA

Field-programmable gate arrays (FGPAs) are widely used because of the superiority in flexibility and lower non-recurring engineering cost. How to optimize the routing architecture is a key problem for FPGA architects because it has a large impact on FPGA area, delay, and routability. In academia, the routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs), whereas most research has focused on SB architectures, such as Wilton, Universal, and Disjoint SB patterns. In this article, we propose a novel unidirectional routing architecture—general interconnection block (GIB)—to improve FPGA performance. With the GIB architecture, logic block (LB) pins can directly connect with the adjacent GIBs without programmable switches. Inside a GIB, LB pins can connect to the routing channel tracks on the four sides of a GIB. In particular, the logic pins from different neighboring LBs that connect to the same GIB can connect with each other with only one programmable switch. In addition, we enhance VTR to support the GIB with bent wires and develop a searching framework based on the simulated annealing algorithm to search for a near-optimal distribution of wire types. We evaluate the GIB architecture on VTR 8 with the provided benchmark circuits. The experimental results show that the GIB architecture with length-4 wires can achieve 9.5% improvement on the critical path delay and 11.1% improvement on the area-delay product compared to the VTR CB-SB architecture with length-4 wires. After exploring mixed wire types, the optimized GIB architecture can further improve the delay by 16.4% and area-delay product by 17.1% compared to the CB-SB architecture with length-4 wires.

A lightweight deployment of TD routing based on SD-WANs

Multipath routing conforms to the evolution principle of network development and is a trend of routing architectures. It can not only meet the needs but also enhance the performance and security of a network. However, deploying multipath routing further increases the scale of the forwarding information base (FIB) and the cost of forwarding devices. Therefore, to realize the lightweight deployment of multipath routing with a distributed architecture, this paper takes two-dimensional routing (TD routing) as an example to provide a solution. We propose a distributed storage mechanism of TD routing in combination with SRv6 (TDSR) and the corresponding SRv6 header (SRH) compression (CARD) method. The main methods are as follows: Inspired by a software-defined wide area network (SD-WAN), this paper introduces segment routing (SR) in the data plane, which can disperse TD-FIBs in different ingress nodes. The ingress routers push path information into the stack, and the intermediate routers forward the packets according to the SRH. Second, for the bandwidth waste of the SRH, compression is attempted by comparing the difference between the the shortest path first (SPF) path and the SRv6 path. Only a few hops in the TD path that are different from those in the one-dimensional (OD) path are kept. Finally, we sort out several typical application scenes of multipath routing and discuss several simplification algorithms. The experimental results show that the TDSR can reduce TD entries by 69%, and the average compression rate of CARD can reach 70%. In addition, CARD can be combined with existing methods to improve their effect.

Arm locking in conjunction with time-delay interferometry

A crucial challenge to the ongoing endeavor of spaceborne gravitational wave (GW) detection resides in the laser phase noise, typically 7 to 8 orders of magnitude above the inevitable noise. The arm locking technique was proposed to suppress the noise in pre-stabilized laser beams. Based on the feedback control theory, it is implemented by appropriate design of the signal routing architecture, particularly the controllers' transfer functions. Theoretically and experimentally, the technique has been demonstrated to be capable of suppressing the laser phase noise by approximately 2-4 orders of magnitude while taking into account various aspects such as the gain and distribution of nulls in the Bode plot and the laser frequency pulling associated with the Doppler frequency subtraction. Consequently, the resultant noise floor is composed of the sources attributed to the clock jitter, optical bench motion, test mass fluctuations, shot-noise phase fluctuations at the photodetectors, whereas the magnitudes of these noises largely remain unchanged during the process. Besides, the original GW signals are deformed through the arm-locking control loop and therefore bear specific features governed by the associated arm-locking scheme. Nonetheless, the remaining laser phase noise from the arm-locking feedback routing settles within the capability threshold of the time-delay interferometry (TDI). In this regard, it is generally understood that the output of arm locking furnishes the input of TDI, through which the residual noise is further reduced to the desired level at a post-processing stage. In this work, we investigate the specific schemes regarding how the arm locking output is processed further by the TDI algorithm. Specific forms of the TDI combinations are derived in accordance with suppressed laser phase noise and deformed signals of GW.

Improved energy-efficient routing architecture for traffic management system using a hybrid meta-heuristic algorithm in Internet of vehicles

Today, Internet of Vehicles (IoV) applications communicate with smart devices and deploy Intelligent Transportation Systems (ITS) to recognize traffic congestion problems. One of the main challenges of smart cities and IoV platforms is data routing methods for smart traffic congestion problems to navigate the individual information of data transmission as a critical issue in the ITS. Providing a way to extend the Quality of Service (QoS) variables and energy efficiency methods for directing data transmission in routing-based traffic management systems within the IoV environment is an important issue since the energy consumption of IoV devices is a critical issue in low-power saving storage. This paper presents a hybrid Genetic Algorithm and Social Spider Optimization (GA-SSO) algorithm for an energy-aware routing schema for optimizing traffic congestion and smart devices in the IoV environment. After conducting some studies and comparisons, the exactness and prevalence of the proposed schema were received. Experimental results confirmed that the GA-SSO algorithm calculation decides optimal and ideal arrangement for energy-aware routing schema demonstrate by essentially making strides the execution of QoS variables can oversee information blockage comes from data transmission between IoV nodes.

A secure cross-layer architecture for reactive routing in vehicle to vehicle (V2V) communications

Vehicular communication is one of the essential technologies for increasing road safety, traffic efficiency, and comfort for pedestrians and drivers. In this context, the internet of vehicles is an emerging paradigm. However, with advances in vehicular communication, security threats have also emerged. Several vulnerabilities exist in vehicular communications, including Denial of Service (DoS), black hole attacks, and fabrication attacks. A malicious attack alters the packet information in a fabrication attack, causing congestion and high delays in the vehicular network. We propose two algorithms to protect the routing protocols in a vehicle-to-vehicle scenario against several attacks that target confidentiality, authentication, privacy, and integrity. The first algorithm detects the malicious behavior of each vehicle by calculating the percentage of modified destination addresses. If it exceeds a predetermined threshold, this vehicle is classified as malicious. Otherwise, it is a normal vehicle. The second algorithm detects malicious modifications based on the Signal to Interference Ratio (SIR) by monitoring the SIR value, adjusting the distance, altering the power received, and changing the transmitted power value. We performed simulations using the SUMO 0.22 simulator and Network Simulator (NS). The results obtained show an improvement in End-to-End (E2E) delay, Packet Delivery Ratio (PDR), and reduced overhead.

Modeling and Empirical Validation of Reliability and Performance Trade-Offs of Dynamic Routing in Service- and Cloud-Based Architectures

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Context:</i> Various patterns of dynamic routing architectures are used in service- and cloud-based environments, including sidecar-based routing, routing through a central entity such as an event store, or architectures with multiple dynamic routers. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Objective:</i> Choosing the wrong architecture may severely impact the reliability or performance of a software system. This article’s objective is to provide models and empirical evidence to precisely estimate the reliability and performance impacts. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Method:</i> We propose an analytical model of request loss for reliability modeling. We studied the accuracy of this model’s predictions empirically and calculated the error rate in 200 experiment runs, during which we measured the round-trip time performance and created a performance model based on multiple regression analysis. Finally, we systematically analyzed the reliability and performance impacts and trade-offs. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Results and Conclusions:</i> The comparison of the empirical data to the reliability model’s predictions shows a low enough and converging error rate for using the model during system architecting. The predictions of the performance model show that distributed approaches for dynamic data routing have a better performance compared to centralized solutions. Our results provide important new insights on dynamic routing architecture decisions to precisely estimate the trade-off between system reliability and performance.

Optimized shortest path algorithm for on-chip board processor in large scale networks

In this paper, we present TriBA (Triplet based) NoC (network on-chip) architecture with 40 nodes referred as TriBA-NoC. TriBA-NoC is implemented in a multi-core 40 tile DDR-3 hardware. The nodes in the TriBA-NoC are connected through recursive triplets. We carried out the performance analysis in network simulator (NS-3) using several perspectives. We adopted TR-132 shortest routing path algorithm with novel router architecture for TriBA-NoC systems. The results of average packet latency for various patterns of traffic of a 40-core TriBA-NoC model are demonstrated. The results of the proposed 40-core TriBA-NoC model achieved better performances while compared to the TriBA.

Comparing timed-division multiplexing and best-effort networks-on-chip

Best-effort (BE) networks-on-chips (NOCs) are usually preferred over time-division multiplexed (TDM) NOCs in multi-core platforms because they are work-conserving and have lower (zero-load) latency. On the other hand, BE NOCs are significantly more expensive to implement than TDM NOCs because of their virtual channel buffers, allocators/arbiters, and (credit-based) flow control; functionality that a TDM NOC avoids altogether.The objective of this paper is to compare the performance of BE and TDM NOCs, taking hardware cost into consideration. The networks are compared using graphs showing average latency as a function of offered load. For the BE NOCs, we use the BookSim simulator, and for the TDM NOCs, we derive a queuing theory model and an associated TDM NOC simulator.Through experiments with both router architectures, packet length, link width, and different traffic patterns, we show that for the same hardware cost, a TDM NOC can provide higher bandwidth and comparable latency. We also show that the packet length is the most important factor affecting the TDM period, which again is the primary factor affecting latency. The best TDM NOC design for BE traffic uses single flit packets, wide links/flits, and a router with two pipeline stages: link and router traversal.

REE: Reconfigurable and energy-efficient router architecture in wireless network-on-chip

Currently, on-chip routers consume the majority of the power budget. Moreover, the static power consumption has taken up a significant fraction of the total power consumption in the router. Especially in the light traffic state, the router idle time is notable, but fragmented owing to the impact of some burst traffic, increasing the challenge of reducing static power consumption through power gating. In this paper, a reconfigurable and energy-efficient router architecture design (REE) is proposed: bypass connections are set for routers, and deflection rules are formulated to ensure that routers maintain connectivity in the network under power gating situation, and reduce the deflection rate of packets encountering sleeping routers. Meanwhile, a reusable predictor is introduced to efficiently predict the idle time to wake up the sleeping router appropriately. In addition, the fine-grained power gating (PG) design is introduced in the wireless interface of wireless routers (WRs) to obtain the scheme REE+, which reduces the idle time of transmitter (TX) components and effectively saves the static power consumption of Wireless Interface. Experiments demonstrate that both the REE and REE + schemes in this paper have negligible impact on latency as well as throughput, while the energy savings are significant: 64.5% and 68.3% average static power savings for REE and REE + schemes, respectively, compared to No_PG, and 13.7% and 20.5% average improvement in terms of static power saving compared to Turn-on on Turn (TooT), respectively.

Research on Generalized Intelligent Routing Technology Based on Graph Neural Network

Aiming at the problems of poor load balancing ability and weak generalization of the existing routing algorithms, this paper proposes an intelligent routing algorithm, GNN-DRL, in the Software Defined Networking (SDN) environment. The GNN-DRL algorithm uses a graph neural network (GNN) to perceive the dynamically changing network topology, generalizes the state of nodes and edges, and combines the self-learning ability of Deep Reinforcement Learning (DRL) to find the optimal routing strategy, which makes GNN-DRL minimize the maximum link utilization and reduces average end-to-end delay under high network load. In this paper, the GNN-DRL intelligent routing algorithm is compared with the Open Shortest Path First (OSPF), Equal-Cost Multi-Path (ECMP), and intelligence-driven experiential network architecture for automatic routing (EARS). The experimental results show that GNN-DRL reduces the maximum link utilization by 13.92% and end-to-end delay by 9.48% compared with the superior intelligent routing algorithm EARS under high traffic load, and can be effectively extended to different network topologies, making possible better load balancing capability and generalizability.

A flexible optical router architecture with modified fuzzy queue based router (FQBR) algorithm for 5G and 6G communication

A flexible optical router architecture with modified fuzzy queue based router (FQBR) algorithm for 5G and 6G communication

FPGA architecture to perform symmetric extension on signals for handling border discontinuities in FIR filtering

This paper proposes a generalized hardware architecture for performing the half-sample and whole-sample symmetric/anti-symmetric extension of a finite-length signal to handle the effect of border discontinuities. The symmetric extension is performed by duplicating the required number of data samples at the boundary followed by reflection about the symmetry axis. The proposed architecture comprises of a shift register that directly streams the data samples, and last-in-first-out (LIFO) buffers to duplicate the data samples at the boundaries. The symmetrically extended signal is obtained by selectively passing the outputs of shift register and LIFO buffers at required instants. Further, a two’s complement circuit is used to invert the data samples at the boundary to perform anti-symmetric extension. The proposed architecture is implemented on field-programmable gate-array (FPGA) to perform the half-sample symmetric extension to favor the low pass Daubechies-8 finite-impulse response (FIR) filter and whole-sample extension for bi-orthogonal 9 × 7 FIR filter with 9 low-pass and 7 high-pass coefficients. The implementation results show that the proposed architecture achieves a maximum operating clock frequency of 275 MHz and 300 MHz for half-sample and whole-sample extension, respectively. The resource utilization of proposed router architecture is approximately reduced by a factor of L (filter length) compared to the conventional router architectures that performs the signal extension by dynamically routing the data samples to the computational part of the FIR filter. The proposed architecture is compatible to various filter architectures without any speed penalty on the performance of FIR filters.