Routing Architecture Research Articles

Dual-Network Layered Network: A Method to Improve Reliability, Security, and Network Efficiency in Distributed Heterogeneous Network Transmission

This article delves into the routing architecture and reliable transmission service framework of dual-network layered networks, with a focus on analyzing their core design ideas and implementation strategies. In the context of increasing network complexity today, traditional single-network architectures are unable to meet diverse application needs. Therefore, dual-network layered networks, as an innovative solution, are gradually receiving attention from both academia and industry. This article first analyzes the key technical elements in the dual-network layered network architecture, including the optimization of routing algorithms, distributed consensus, reliability assurance mechanisms for packet transmission, and dynamic allocation strategies for network resources. Through in-depth research on these technologies, this article elaborates on the important role of dual-network layered networks in building efficient and stable transmission environments, providing important theoretical foundations and technical support for the construction and optimization of future network systems.

Compact multi-port multi-wavelength laser source with Tbps transmission for optical I/O technology.

In this paper, we propose and experimentally demonstrate a novel compact multi-port multi-wavelength laser source (MP-MWL) for the optical I/O technology. The multi-wavelength DFB laser array is used for realizing the simultaneous emission of multiple wavelengths. The reconstruction equivalent chirp technique is used to design and fabricate the π-phase shifted DFB laser array to achieve precise wavelength spacing. The number of wavelengths is enlarged through the monolithically integrated wavelength routing architecture (WRA), and 64 optical carriers are obtained with 8 wavelengths in 8 output ports. The proposed MP-MWL has high mode stability and high uniform wavelength spacing. The side mode suppression ratio (SMSR) of each wavelength is more than 40 dB and the wavelength spacing is 100 GHz under 25 °C working environment. A semiconductor optical amplifier (SOA) is monolithically integrated into each output port to amplify the output power. The output power of each port exceeds 15 mW when the current injected into the SOA is 150 mA. Besides, the relative intensity noise (RIN) of all wavelengths is below -130 dB/Hz, and clear 25 Gb/s NRZ eye grams are obtained for the 64 optical carriers with the external lithium-niobate Mach-Zehnder modulator, with a total transmission rate of 1.6 Tbps. The superior performance of the proposed MP-MWL enables it to be a promising approach for the Tbps optical I/O links and high-density chip interconnection system.

Design of Area Efficient Network-On-Chip Router: A Comprehensive Review

The number of uses for cutting-edge technologies has led to a further growth in a single chip's computational capacity. In this case, several applications want to build on a single chip for computing resources. As a result, connecting the IP cores becomes yet another difficult chore. The many-core System-On-Chips (SoCs) are being replaced by Network-On-Chip (NoC) as an on-chip connectivity option. As a result, the Network on Chip was created as a cutting-edge framework for those networks inside the System on Chip. Modern multiprocessor architectures would benefit more from a NoC architecture as its communication backbone. The most important components of any network structure are its topologies, routing algorithms, and router architectures. NoCs use the routers on each node to route traffic. Circuit complexity, high critical path latency, resource usage, timing, and power efficiency are the primary shortcomings of conventional NoC router architecture. It has been difficult to build a high-performance, low-latency NoC with little area overhead. This paper surveys previous methods and strategies for NoC router topologies and study of general router architecture and its components. Analysis is carried out to understand and work for a low latency, low power consumption, and high performance NoC router design that can be employed with a wide range of FPGA families. In the current work, we are structuring a modified four port router with the goals of low area and high performance operation.

Optimal scheduling of energy routers based on distributed CAES systems

Abstract With the rise of renewable energy, distributed energy, and other different forms of energy, the architecture and function of the energy router are relatively perfect, for the topology of the energy router itself, different forms of energy in the energy router flow, conversion to realize the large-scale use of distributed energy equipment has also gradually become a hot spot of research. However, there are fewer studies on the energy router with a distributed CAES system to participate in the optimal scheduling of energy for integrated energy systems. Therefore, this paper is based on the operational domain model of an energy router with a distributed CAES system and analyzes the physical characteristics and coupling relationship of non-energy storage components, takes air pressure, temperature, and oil volume as state variables, takes charging, power generation, and heating power as external interfaces, and utilizes internal interface variables such as air quality and flow rate to realize energy storage, flow, and other internal interface variables to realize the communication between energy storage and non-energy storage elements, and finally determine the operation domain of the system. Secondly, the feasible domain of the energy router based on the distributed CAES system is portrayed, and the optimization of the system parameters is guided with the help of the relative distance by establishing the electric and thermal power constraints and the storage state constraints. Finally, the effectiveness of the feasible domain analysis method in the energy router of a distributed CAES system is verified by taking a northern region as an example.

Light Weight Concurrent Scheduling of Mobile Sink routing protocol towards Minimization of Propagation Delay against Spatial and Temporal Uncertainties of Cluster based Wireless Sensor Network

Wireless Sensor Network highly exposed to certain security attacks due to various uncertainties of the network which lead to node compromise. Hence considerable attention has been made by researcher during scheduling of the mobile sink to data collection of sensed information from the sensor nodes. Many secure data aggregation mechanism has been proposed to withstand the network against these kind of attack. Despite of many advantageous, those architectures will lead to several limitations such as large propagation delay and high energy consumption and spatial and temporal uncertainties. In order to mitigate those challenges, Light Weight Concurrent Scheduling of Mobile Sink routing protocol towards Minimization of Propagation Delay against Spatial and Temporal Uncertainties of Wireless Sensor Network is designed. It should be capable achieving energy efficiency and collision avoidance due to uncertainty in transmission and reception. Proposed model eliminates the packet collision and poor channel utilization challenges. Initially, node is partitioned and cluster head is selected based on the highest energy density of the node in the particular location. Employing Full duplex channel easily examines the spatial and temporal characteristic of the node through utilization cache information of routing table. It further helps to build the light weight scheme with behavioral strategies of the nodes for secure propagation of the sensed data to the mobile sink. Light weight scheme deployed in mobile sinks estimate the node trustworthiness and simultaneously collects the secure aggregated data packets of the sensor node through cluster head against dynamic time slots concurrently .Comparing with traditional secure routing architecture, simulation results demonstrates that proposed architecture can reduce the propagation delay against various uncertainties and maximizes the life time of the network on increasing the networking performances with respect to packet delivery ratio, throughput and propagation delay. Finally proposed model obtains the cooperative communication of sensor node information to the base station through mobile sink on heterogeneous wireless sensor network environment. DOI: https://doi.org/10.52783/pst.387

SPONGE+: A NoC-based power gating scheme for overall router column opening and closing control

Power gating, a general-purpose power saving technique, can be used to turn off inactive routers in Networks-on-Chip (NoCs) to reduce static power consumption. SPONGE is an advanced power gating scheme. When the router is dormant, SPONGE maintains the transmission of straight packets, which occupy a large percentage of the network, through a direct bypass design. At the same time, the energized router column’s can ensure the normal transmission of turning packets. However, it suffers from increased latency due to excessive detours, aggravated load imbalance, and violation of the breakeven time (BET) constraint. To address the above problems, we propose an improved energy-efficient router architecture SPONGE+. First, we design a new router bypass architecture that enables powered-off routers to have the ability to transmit straight ahead and turn in the X-to-Y direction to reduce the bypass cost of packet transmission. Secondly, we propose a congestion-aware turning routing algorithm to balance the load among powered-on routers and improve network resource utilization. Finally, we pin improves the power gating mechanism for router columns to satisfy the BET constraint and further reduce the static power expenses. Experimental results indicate that, under real application scenarios, our scheme achieves a 27.3% reduction in static power consumption and a 10.5% decrease in packet latency compared to SPONGE, with commendable scalability.

A tree-recursive partitioned multicast mechanism for NoC-based deep neural network accelerator

In chip multiprocessor systems (CMPs), Network on Chip (NoC) has been widely used due to its advantages of favorable reusability, high reliability, and low power consumption. Recently, using NoC platforms to accelerate deep neural networks (DNNs) has become a new trend. This design can enable the intermediate computation results of DNNs to be transmitted within the chip, reducing the number of accesses to off-chip memory. However, a large amount of one-to-many traffic in the DNN accelerator will occupy the system bandwidth, which will significantly reduce the performance of the NoC platform dominated by one-to-one traffic. To address this issue, we propose a tree-based recursive partitioning multicast scheme (TRPM), which increases the path diversity and improves the system bandwidth. We also design a single-cycle per-hop router architecture, which effectively enhances the transmission efficiency of multicast packets. Detailed simulation results show that compared with the latest tree-based multicast algorithm for DNN accelerators, our scheme reduces the number of routed packets by 35%, the classification latency by 13.5% and the average packet latency by 14.5% on average.

An Efficient FPGA Architecture with Turn-Restricted Switch Boxes

Abstract. Field-Programmable Gate Arrays (FPGAs) employ a large number of SRAM cells to provide a flexible routing architecture which have a significant impact on the FPGA’s area and power consumption. This flexible routing allows for a rather easy realization of the desired functionality, but our evaluations show that the full routing flexibility is not required in many occasions. In this work, we focus on what is actually needed and introduce a new switch-box realization what we call Turn-Restricted Switch-Boxes which supports only a subset of possible turns. The proposed method increases the utilization rate of FPGA switch-boxes by eliminating the unemployed resources. Experimental evaluations confirm that the area and average power consumption can be reduced by 12.8% and 14.1%, on average, respectively and the FPGA routing susceptibility to SEU and MBU can be improved by 18.2%, on average, by imposing negligible performance. 1

AS-Router: A novel allocation service for efficient Network-on-Chip

Assigning input ports to output ports and allowing flits to pass through the switch without colliding is accomplished by Switch Allocation (SA), a crucial pipeline stage in the Network-on-Chip (NoC) router. Earlier research improved the efficiency of matching to enhance SA processes. The studies in question, however, failed to account for the importance of information sharing between the various phases of the router’s pipeline. To improve NoC routers’ allocation, this article introduces the Allocation Service (AS) concept. By adding a new pipeline stage called Request Finalization (RF) before the SA stage, the AS can be optimized. The RF stage’s objective is to complete the uniform request and Endpoint Congestion Causing (EPC) requests for SA before sending them on their way. These results inform the proposal of a new design, the CUE-Router, to increase AS by the integration of an RF stage and inter-pipeline communication between routers. Two new types of router architecture form the basis for CUE-Router. The first thing we do in this work is introduce URR-Router, a router that only allocates EPC requests if there are no uniform requests in the SA stage, effectively giving uniform requests a priority. The second example is the EPR-Router, which alleviates endpoint congestion by favoring EPC requests over uniform ones. In this work, we take a fresh look at the SA process optimization that underpins the low-latency CUE-Router architecture by cycling through a series of prioritization changes between uniform requests and EPC requests. CUE-Router greatly improves SA efficiency and network performance by facilitating communication between the various stages of the pipeline. Based on the results of the analysis, our approach has the potential to significantly enhance performance with minimal additional effort.

Applying SMART-Based Power Gating Approach in NoC System

SMART is a low-latency solution that transmits nonconflicting flits to remote routers, enabling traversal of multi-hop paths within a single cycle. It reduces packet latency but ignores high power consumption in idle components. Additionally, SMART’s low latency is highly dependent on [Formula: see text], which represents the maximum number of hops traversed within a cycle. Therefore, this paper presents SMART-PG, a power gating method based on SMART that reduces network power consumption by shutting down idle components such as router buffers under low-load conditions. We also extend the router architecture to enable the continuous establishment of single-cycle multi-hop bypass paths. Compared to SMART routers, our method eliminates packet buffering even when a packet reaches the last router of a single-cycle multi-hop path, reducing packet latency and sensitivity to [Formula: see text]. Finally, we propose a routing algorithm that enables efficient packet transmission in one-dimensional and two-dimensional networks even when routers are powered off. Experimental results show that our method reduces packet latency and static power consumption by an average of 7.5% and 46.4%, respectively, compared to the baseline router. Compared to SMART routers, our method demonstrates significant superiority in terms of packet latency and the impact of multi-hop length on packet latency.

A multi-type semantic interaction and enhancement method for tax question understanding

Problem classification serves as a fundamental process in a tax intelligence consulting system, enabling the categorization of user-posed questions according to their semantic attributes. This categorization is pivotal in ensuring accurate question comprehension. Nevertheless, the inclusion of intricate professional terminology and the frequent alterations in linguistic structures associated with tax-related matters may culminate in suboptimal classification outcomes and hinder the precise comprehension of user demands. To address these issues, we propose a multitype semantic interaction and enhancement method (MtSIEM) to classify tax related issues that integrates entity and nonentity semantics to represent the semantic features of tax-related domain issues. Specifically, a pretraining language model and multigram mechanism are adopted to enhance the feature extraction ability. A soft attention module is also simplified to allocate interaction information weights, thereby adaptively determining the importance of the feature elements. These three components are used to perform precise learning on the tax question data. Subsequently, a dynamic routing architecture is employed to capture the relationships between the different problem features, resulting in predictive vectors. A series of comparative experiments on tax question data demonstrated that the proposed model achieved a classification accuracy of approximately 94.46%, an improvement of 2.99% compared with the baseline. Therefore, the proposed model can be utilized to predict the semantic category of tax-related issues, assisting intelligent tax advisory systems in matching questions with the most relevant knowledge and professional domains, thereby enabling faster retrieval of pertinent information and enhancing the timeliness of responses.

Design a patient monitoring system in health care using cluster-based hierarchical routing for green communication

To achieve a healthcare patient monitoring system, this paper presents a clustering-based hierarchical approach. A group-based controlled structured routing architecture is used in the proposed method to group the various health monitoring sensors. A merged center will select a leader for each cluster and delegate the management responsibilities to that individual. Collecting information, organizing, and communicating with leading platforms are all the responsibilities of the cluster leader. The goal of this rotation is to keep the system under a constant load and to optimize the efficiency of the support equipment. A large number of simulations were used to validate our quantitative approach, and we compared our results with other methods already in use. Our study confirms that our approach not only reduces the energy required to maintain the network in various configurations, but also significantly increases their lifetime. The QoD of our proposed method was 4.9 %, compared with the QoD of 7.45 % and 9.82 % for DEEC and LEACH, respectively. Demonstrated that cluster-based hierarchical roads can enable a healthcare patient monitoring system.

Multi-modal fusion architecture search for camera-based semantic scene completion

Camera-based Semantic scene completion (SSC) aims to infer the 3D volumetric occupancy and semantic categories of a scene simultaneously from a single RGB image. The main challenge of camera-based SSC is the lack of geometry information compared with RGB-D SSC. Although the estimated depth from RGB image will help SSC to some extent, the depth prediction quality is far from the demand of SSC. To solve this problem, we propose a NAS-based multi-modal fusion method to incorporate the semantic and geometry information from other intermediate representations (predicted depth and predicted 2D segmentation) to form a more robust 2D feature representation. A key idea of this design is that explicit 2D semantic information could alleviate the misleading information of 3D distortions introduced by estimated depth. Specifically, we propose the Confidence-Block to automatically learn an optimal architecture for routing and obtaining the depth prediction confidence. We propose the two-level fusion search space by decomposing the fusion search space into fusion stage search space and fusion operation search space. Moreover, we propose a confidence-aware 2D–3D projection module to alleviate the 3D projection error. Extensive experiments show that our method outperforms the state-of-the-art method by a large margin using a single RGB image on NYU and NYUCAD datasets.

Evidence for increased parallel information transmission in human brain networks compared to macaques and male mice

Brain communication, defined as information transmission through white-matter connections, is at the foundation of the brain’s computational capacities that subtend almost all aspects of behavior: from sensory perception shared across mammalian species, to complex cognitive functions in humans. How did communication strategies in macroscale brain networks adapt across evolution to accomplish increasingly complex functions? By applying a graph- and information-theory approach to assess information-related pathways in male mouse, macaque and human brains, we show a brain communication gap between selective information transmission in non-human mammals, where brain regions share information through single polysynaptic pathways, and parallel information transmission in humans, where regions share information through multiple parallel pathways. In humans, parallel transmission acts as a major connector between unimodal and transmodal systems. The layout of information-related pathways is unique to individuals across different mammalian species, pointing at the individual-level specificity of information routing architecture. Our work provides evidence that different communication patterns are tied to the evolution of mammalian brain networks.

Round Robin based Arbitration Mechanism for Signaling Approach based Router Architecture

In Network-on-Chip the effectiveness of the network resource allocation is demonstrated by the flow control mechanism. There are two types of flow control mechanisms: buffered and bufferless. Compared to buffered flow control methods, buffer less flow control mechanisms are easier to use, need less power, and take up less space. When there are congestion and resource conflicts, it experiences higher packet loss and packet misrouting inside the network. A good buffered control mechanism useful as it overcomes the limitations of buffer less mechanism. There are numerous buffered and bufferless flow control methods available. In this paper, signaling-based Virtual Output Queue Router Arbiter Mechanism is used to explore credit-based flow control. This mechanism worked on new concept that is “stress value”. This information is generated in the form of credit whenever any input buffer has free space. Then, using this credit data, the node's stress value is determined. Free buffer space takes precedence over stress value if it is bigger. The stress value will increase if there is less available buffer space. To handle the congestion problem, the signaling block then sends this stress value to a neighboring router. To help the arbitrator make a more accurate decision, the crediting system constantly operates in tandem with arbitration.

Intelligent edge network routing architecture with blockchain for the IoT

The demand for the Internet of Everything has slowed down network routing efficiency. Traditional routing policies rely on manual configuration, which has limitations and adversely affects network performance. In this paper, we propose an Internet of Things (IoT) Intelligent Edge Network Routing (ENIR) architecture. ENIR uses deep reinforcement learning (DRL) to simulate human learning of empirical knowledge and an intelligent routing closed-loop control mechanism for real-time interaction with the network environment. According to the network demand and environmental conditions, the method can dynamically adjust network resources and perform intelligent routing optimization. It uses blockchain technology to share network knowledge and global optimization of network routing. The intelligent routing method uses the deep deterministic policy gradient (DDPG) algorithm. Our simulation results show that ENIR provides significantly better link utilization and transmission delay performance than various routing methods (e.g., open shortest path first, routing based on Q-learning and DRL-based control framework for traffic engineering).

Router forensics: Navigating the digital crossroads

As the digital landscape continues to evolve, routers have become central gatekeepers, governing the flow of information in networks. This study delves deep into the realm of router forensics, focusing on the methodologies and techniques employed to extract and analyze forensic data from these pivotal devices. Drawing upon both traditional and contemporary approaches, our research underscores the significance of router logs, volatile data, and the challenges that arise in their forensic analysis. We highlight the pressing need for standardized forensic protocols, especially in the face of diverse router architectures and rapidly emerging cyber threats. Our study also emphasizes the potential of leveraging advanced technologies, such as machine learning, in enhancing forensic capabilities. By providing a comprehensive overview of the current state of router forensics and shedding light on potential future trajectories, this research aims to fortify the cybersecurity community's arsenal against escalating cyber threats, ensuring a more secure and resilient digital ecosystem.

Design and Analysis of Four Port Router for Network-On-Chip Applications

System-On-Chip (SoC) is a popular VLSI technology that integrates multiple devices onto a single chip. The Network-On-Chip (NOC) concept, which is a novel paradigm in sophisticated System-On-Chip designs that offers efficient communication throughout the on-chip networks, is used to communicate amongst various devices. The router is the main component in an NoC architecture that is responsible for routing information. Packets are sent through a network by an NoC made up of routers. A routing algorithm divides packets into flow control digits (flits) and determines their paths. The placement of routers is determined by the network topology. In the present work, the main target is to design and analyse the router, which is primarily based on a number of critical factors, including topology, routing algorithm, and packet format. The performance of the suggested router is evaluated and compared to that of the Conventional Wormhole Router (CWHR) with respect to power and slack time (ST). When compared to a traditional wormhole router, the proposed router architecture has 18% less slack. As a result, total power consumption is reduced by 29.3% as compared to traditional wormhole architecture. The architecture is synthesized using Cadence Encounter RTL Compiler using standard 65nm technology.

Selective wakeup for parallel forward engines under variable load towards energy conservation in IP routers

SummaryRecent studies have shown that a large amount of energy consumption in the communication medium occurs at the data processing plane. The data plane executes the forwarding decisions in the routers and switches. Through initial studies, the line card was identified as the most granular component of the router and later forward engine, a sub component of line card has been recognized as the most power intensive component of routers. Fundamental techniques like link rate adaption, sleep and wake‐up have been imposed to reduce the energy at line cards and forward engines. On the other hand, router's architectures undergo drastic changes like empowering data plane with parallel processing due to the rise of gigabit routers. In this paper, to increase the degree of local autonomy and better energy savings, we have adopted the parallel processing design and imposed a variable amount of traffic on different line cards. The existing parallel forward engines perform load balancing in synchronous manner. In our design, asynchronous behavior is imposed such that every line card could independently decide to wake up or turn off their forward engine based on the traffic parameters. We have done simulations and witnessed increased energy savings (average sleeping time) without compromising the completion of lookup process.

Adopting a Standard Track Routing Architecture for Next-Generation Hybrid AC/DC-Biased Logic Circuits

The adiabatic quantum-flux-parametron (AQFP) and rapid single flux quantum (RSFQ) logic families both provide distinct advantages for data processing using superconductor electronics. The development of next-generation AQFP-RSFQ hybrid logic circuits provides the opportunity to combine the benefits of both of these logic families. Adopting a standard track routing architecture for both AQFP and RSFQ layouts provides a unified framework for physical layout synthesis. We demonstrate a standard track routing architecture developed under the ColdFlux project and its implementation within AQFP. An additional advantage of the standard track routing architecture is that it provides a systematic way to overcome metal density requirements for modern-day fabrication processes. It also provides a methodical approach towards strategic moat placement for protection against unwanted flux trapping. Implementations of passive transmission line (PTL) connections and their physical placement for hybrid AQFP-RSFQ circuits are discussed. Several AQFP layouts for the ColdFlux project are redesigned to adopt the standard track routing architecture. Experimental simulation of moat performance is also presented.