Robust Interconnection Research Articles

Robust Interconnects and Packaging for Microfluidic Elastomeric Chips

A stable, rugged, and easy-to-use microfluidic platform has been developed and evaluated. The system is based on multilayer silicone elastomer chips with integrated flow channels and active components, such as pressure-actuated valves. The silicone chips and stainless steel interconnect tubes are embedded in a block of an epoxy resin to give the chip and the interconnects outstanding mechanical stability. Full optical accessibility of the chip for demanding optical detection and manipulation applications, such as fluorescence and bright-field microscopy and optical tweezing, is achieved through the use of an optically transparent epoxy resin and microscope cover glasses as the packaging materials. Furthermore, this packaging technique uses a purely mechanical seal between the elastomer and cover glass, enabling applications that use chemically functionalized glass surfaces as the bottom of the flow channels. In addition, a socket was developed in which the microfluidic chips can be plugged in to provide a...

A Robust Multilevel Interconnect Module for Subquartermicrometer Complementary Metal Oxide Semiconductor Technology Integration

In this work, we present detailed studies of two integration schemes for an aluminum-wire/tungsten-plug-based multilevel ultralarge scale integration (ULSI) interconnect module for subquartermicrometer complementary metal oxide semiconductor (CMOS) technologies, and discuss the benefits and drawbacks of each of them primarily from a process integration point of view. We demonstrate that an etch stop (ES) integration scheme in which the via etch stops on the TiN cladding layer could result in significantly improved via electromigration performance compared to an over etch (OE) integration scheme in which the via is overetched into the underlying Al(Cu). We also identified several highly detrimental early failure modes associated with the OE structure, including contamination-induced stress void formation underneath the via, the metal extrusion inside the via, and the metal corrosion at the bottom of the via, and showed that such early failure modes could be prevented in the ES integration scheme. Even though there were some small penalties in the device performance in the ES integration scheme, the benefits in the reliability and the better tolerance to manufacturing process variation clearly justify the adoption of this robust multilevel ULSI interconnect module for subquartermicrometer CMOS technologies. © 2002 The Electrochemical Society. All rights reserved.

Model for metal interconnection design rule optimization

Joule heating for short time pulses causing internal breakdown of metal interconnects in ESD/EOS protection circuits and I/O buffers has been analyzed. A model has been developed for the optimization of design rules by incorporating maximum allowable current density, the geometry and type of metal lines, surrounding oxide layer and pulse width The model shows good agreement with the experimental results and can be used to generate robust interconnection design guidelines for ESD/EOS and I/O buffers.

Development of robust interconnect model based on design of experiments and multiobjective optimization

When designing an integrated circuit, it is important to take into consideration random variations arising from process variability. Traditional optimization studies on VLSI interconnect attempt to find the deterministic optimum of a cost function but do not take into account the effect of these random variations on the objective. We have developed an effective methodology based on TCAD simulation and design of experiments to optimize interconnect including the effects of process variations. The aim of the study is to search for optimum designs that both meet the performance specification and are robust with respect to process variations. A multiobjective optimization technique known as Normal Boundary Intersection is used to find evenly-spaced tradeoff points on the Pareto curve. Designers can then select designs from the curve without using arbitrary weighting parameters. The proposed methodology was applied to a 0.12 /spl mu/m CMOS technology; optimization results are discussed and verified using Monte Carlo simulation.

IPCs with conventional or electronically switched phase shifting devices

Unified power flow controllers and interphase power controllers (IPC) are power system devices for the load flow management of AC systems. This article discusses different theoretical and practical aspects of the IPC, which is a robust series controller and interconnection device consisting in each phase of two parallel impedances-one inductive and the other capacitive. The two impedances are normally connected in series to two phase-shifted voltages. The phase-shifting devices can be conventional or electronically switched phase-shifting transformers.

Modeling and microstructural characterization of incubation, time-dependent drift and saturation during electromigration in Al–Si–Cu stripes

Resistance data of passivated Al–Si–Cu contact electromigration test structures clearly show three different stages: incubation, time-dependent drift and ultimately saturation. A detailed model describing all three stages was developed and evidenced by a thorough analysis of the tested material. By using this model, a length dependent lifetime can be calculated and data obtained from different test structures can be compared directly with each other. Moreover, it can be predicted that due to the length dependent saturation, lines below a certain length will never reach the failure criterion! Taking this information into account during the design phase leads to very robust interconnects.

An all-purpose transmission-line model for interconnect simulation in SPICE

A new all-purpose multiconductor transmission-line model is described for efficient and robust interconnect simulation using nonlinear circuit simulators such as SPICE. All types of interconnects, i.e., uniform, nonuniform, lossless, lossy/dispersive, can be handled by the proposed model. Furthermore, coupling of electromagnetic radiation to interconnects can be directly modeled without the need for developing a new subcircuit. Another advantage of the proposed model is that it enables sensitivity analysis with respect to both circuit and interconnect parameters, thus facilitating interconnect circuit optimization. Chebyshev expansions for the spatial variations of the interconnect voltages and currents are used to effect highly accurate numerical approximations of the Telegrapher's equations using as small a number of degrees of freedom as possible. A simple rule of thumb is provided for the selection of the order of the approximation given the frequency bandwidth of interest. Numerical examples are presented to demonstrate the validity of the proposed model and illustrate its application to a variety of interconnect-induced noise interactions in high-speed electronic systems.

Multi-level interconnects for heterojunction bipolar transistor integrated circuit technologies

Heterojunction bipolar transistors (HBTs) are mesa structures which present difficult planarization problems in integrated circuit fabrication. We report a multilevel metal interconnect technology using benzocyclobutene (BCB) to implement high-speed, low-power photoreceivers based on InGaAs/InP HBTs. Processes for patterning and dry etching BCB to achieve smooth via holes with sloped sidewalls are presented. Excellent planarization of 1.9 μm mesa topographies on InGaAs/InP device structures is demonstrated using scanning electron microscopy (SEM). Additionally, SEM cross-sections of both the multi-level metal interconnect via holes and the base-emitter via holes required in the HBT 1C process are presented. All via holes exhibit sloped sidewalls with slopes of 0.4 μm μm −1 which are needed to realize a robust interconnect process. Specific contact resistances of the interconnects are found to be less than 6 × 10 −8 Ω cm 2. Integrated circuits utilizing InGaAs/InP HBTs are fabricated to demonstrate the applicability and compatibility of the multi-level interconnect technology with integrated circuit processing.

Packaging of glass waveguide silicon devices

We demonstrate a technique that makes possible the robust packaging and interconnection of fiber pigtails to glass waveguide silicon devices. An integrated 19 x 19 star coupler, formed on a silicon substrate, is covered with a silica slab attached by means of a low-index epoxy. The slab both isolates the waveguides, which are just a few micrometers below the surface, from their surroundings and provides a means for attaching fiber connectors. Measurements of the performance of the star coupler before and after covering even show a slight (<0.5 dB) improvement for many of the waveguides due to the silica cover.

Coupled transport/chemistry calculations on the massively parallel processor computer

Coupled transport/chemistry problems are performed on the Massively Parallel Processor (MPP) computer. The MPP is a single-instruction multiple data (SIMD) machine with 16,384, individual processors arranged in a 2-D array with nearest neighbor connections between processors. The suitability of this architecture for coupled/transport chemistry applications is investigated. Substantial speedups can be achieved on the MPP when concurrency in the calculation can be exploited. For example, speedup factors on the MPP of 450 and 10 relative to VAX 11/780 and Cray-2, respectively, are achieved for 3-D chemistry calculation. Various aspects of parallel computing on the MPP are discussed. Transport/chemistry calculations have been performed on the NASA/Goddard MPP computer. The MPP is a SIMD machine with 16,384 individual processors arranged in a 2-D array with nearest neighbor connections between processors. This architecture is well-suited for performing chemical calculations arising from 3-D transport/chemistry problems. When operator splitting techniques are used, then each grid point in a 3-D domain can be mapped to a processor, and the chemistry at each grid point calculated in parallel. Speedup factors of over 450 and 10 were achieved on the MPP relative to the VAX 11/780 and Cray-2, respectively for the chemistry calculations. The MPP is also well-suited for 2-D transport calculations. However, due to the 2-D physical arrangement of the processor, 3-D transport problems are more difficult on the MPP. These test calculations suggest that the MPP and similar machines are well-suited for coupled transport/chemistry applications and that more robust interconnect topologies (e.g. hypercube) are needed. However, further work is necessary to gain the knowledge and experience necessary to fully exploit these machines and to evaluate their utility.

An 0(n2.5) Fault Identification Algorithm for Diagnosable Systems

Consider a system composed of n independent processors, each of which tests a subset of the others. It is assumed that at most tp of these processors are permanently faulty and that the outcome of a test is reliable if and only if the processor which performed the test is fault free. Such a system is said to be tp-diagnosable if, given any complete collection of test results, the set of faulty processors can be uniquely identified. In this paper, it is shown that tp-diagnosable systems, due to their robust interconnection structure, possess heretofore unknown graph theoretic properties relative to vertex cover sets and maximum matchings. An 0(n2.5) algorithm is given which exploits these properties to identify the set of faulty processors in a tp-diagnosable system. The algorithm is shown to be correct, complete, not based on any conjecture, and superior to any other known fault identification algorithm for the general class of tp-diagnosable systems.