Rm DD Research Articles

Probing the Roton Excitation Spectrum of a Stable Dipolar Bose Gas.

We measure the excitation spectrum of a stable dipolar Bose-Einstein condensate over a wide momentum range via Bragg spectroscopy. We precisely control the relative strength ε_{dd} of the dipolar to the contact interactions and observe that the spectrum increasingly deviates from the linear phononic behavior for increasing ε_{dd}. Reaching the dipolar-dominated regime ε_{dd}>1, we observe the emergence of a roton minimum in the spectrum and its softening towards instability. We characterize how the excitation energy and the strength of the density-density correlations at the roton momentum vary with ε_{dd}. Our findings are in excellent agreement with numerical calculations based on mean-field Bogoliubov theory. When including beyond-mean-field corrections, in the form of a Lee-Huang-Yang potential, we observe a quantitative deviation from the experiment, questioning the validity of such a description in the roton regime.

Power Consumption Model for AMOLED Display Panel Based on 2T-1C Pixel Circuit

The display device has a significant contribution to the total power, which is critical for mobile consumer-electronic devices due to a limited battery capacity. We develop a power model of the active-matrix organic light-emitting diode (AMOLED) display and analyze the power contribution of thin-film transistor (TFT), OLED, and ${V_{\rm DD}}$ line drop. Both theoretical analysis and calculation are derived from TFT mobility, OLED luminous efficiency, pixel aperture ratio, and ${V_{\rm DD}}$ line drop. The TFT mobility from ${0.1}$ to ${10}\; \text{cm}^{2}/(\text{V}\cdot \text{s})$ is a bottleneck of display power. Metal oxide TFT may be more suitable for AMOLED display since relatively high mobility and low fabrication temperature. High luminous efficiency of OLED and top emission structure can decrease power consumption abundantly. The impact of copper wire technology is also discussed in large-size panels.

A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM

The impact of device variability, temperature, and technology CAD-based layout parasitics on low-voltage static random access memory (SRAM) yield is explored using a novel variability-aware statistical methodology. Threshold voltage, $V_{t}$ , mismatches for planar 22- and 14-nm FinFET SRAM transistors are characterized based on unique array-like structures for capturing process voltage and temperature (PVT) impact on variability. In general, the mismatches are shown to be a consistent and unique function of $V_{\rm dd}$ , doping, and temperature across the two technologies. Stronger $V_{t}$ mismatch impact is observed as a function of $V_{\rm dd}$ and doping in the 22-nm technology, with higher mismatch recorded at lower temperatures. In the 14-nm technology, doping is found to have the strongest impact on $V_{t}$ mismatch, and the mismatch increases with $V_{\rm dd}$ despite the reduced drain-induced barrier lowering effects. Similar to the 22-nm technology, the mismatch increases at lower temperatures. Front-end-of-the-line capacitance effects are found to be more significant than back-end-of-the-line effects in 14-nm technologies, as opposed to planar technologies. Accurate parasitic capacitance modeling along with PVT-aware variability process variations for different 22-/14-nm cell arrangements are incorporated into a physics-based statistical analysis methodology for accurate $V_{\rm min}$ analysis. The yield analysis results are corroborated with hardware yield using 4–16-Mb inline SRAM macro monitors. The methodology is unique in the industry, gives insight into the technology-circuit interactions, and is able to effectively predict the SRAM yield bounds.

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache

In this paper, we investigate the feasibility of voltage adjustment in a large capacity cache, and propose the architecture of voltage-adaptable nonuniform cache access (VANUCA) that exploits near-threshold computing and multivoltage domain to approach the limit of $V_{\rm dd}$ in a low-power cache. However, the adoption of near-threshold voltage (NTV) leads to a rocketing error probability in SRAM arrays, which has to be addressed by effective fault-tolerant techniques. Instead of using error correction code or data duplication, the VANUCA exploits the natural data redundancy across the whole memory hierarchy to enable fast fault recovery in the NTV cache. Based on the discovered data resilience and the multi- $V_{\rm dd}$ architecture, the VANUCA is able to match vulnerable/invulnerable data clusters to available high-/low-voltage domains by utilizing the data migration mechanism in dynamic NUCA. The proposed VANUCA includes two important architectural techniques: 1) static assignment that assumes a fixed voltage domain partitioning and 2) DataMotion that dynamically fits the working set into heterogeneous cache banks through $V_{\rm dd}$ switching. Experimental results show that the VANUCA achieves considerable improvements in energy efficiency over the conventional single-voltage domain NUCA cache.

Effect of Metal Gate Granularity Induced Random Fluctuations on Si Gate-All-Around Nanowire MOSFET 6-T SRAM Cell Stability

In this paper, we present a variability-aware 3-D mixed-mode device simulation study of Si gate-all-around (GAA) nanowire mosfet (NWFET)-based 6-T static random access memory (SRAM) bit-cell stability and performance considering metal-gate granularity (MGG) induced intrinsic device random fluctuations and quantum corrected room temperature drift-diffusion transport. The impact of MGG contributed intrinsic variability on Si GAA n- and p-NWFETs-based SRAM cell static noise margins (SNM), write and read delay time are statistically analyzed. Our statistical simulations predict acceptable stability for the Si NWFET 6-T SRAM cell with $V_{{\rm DD}}$ downscaling up to 0.5 V. The simulation estimated mean hold SNM values follow a lowering trend with $V_{{\rm DD}}$ downscaling, similar to the hold SNM experimental data reported in the literature for Si GAA NWFET-based SRAM arrays. We further show a linear variation in statistical variance of hold SNM with gate metal grain size and work function.

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations

Interconnect opens are a major class of defects found in today’s nanometer technologies. These defects present subtle behavior that could lead to test escapes and hence compromise test quality. Furthermore, they could become a reliability risk. Low-voltage testing has been suggested as a static test to improve the defect coverage of interconnect opens. In nanometer technologies, process variability is predominant and considering only the nominal value of parameters is not realistic. Hence, process variations should be considered to analyze the behavior of interconnect opens. In this brief, the detection capabilities of low-voltage testing for interconnect opens considering process variations is investigated. A statistical model is used for the interconnect open defect. Correlation between parameters of the affected gates and spatial correlation of the parameters for those gates tied to the defective floating node have been considered. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS85 benchmark circuits. Based on these results, it is suggested to use low $V_{\rm DD}$ in conjunction with favorable logic conditions at the coupling lines to enhance the defect coverage of interconnect opens leading to better test quality and higher product reliability.

Wideband Balanced Network with High Isolation Using Double-Sided Parallel-Strip Line

A new wideband balanced power dividing/combining network with high isolation is proposed in this paper. The differential/common mode equivalent circuits of the balanced network can be easily reduced based on the matrix transformation. Two double-sided parallel-strip line (DSPSL) 180 $^{\circ}$ phase inverters loaded with four isolation resistors are used to realize high isolation for the power division output ports. A planar wideband balanced network with bandwidth 52.7% of (1.68–2.84 GHz, $\vert S_{{\rm dd}21}, S_{{\rm dd}31}\vert >- 4$ dB) for the differential mode and high isolation for the differential/common mode is designed and fabricated. The measured results show good agreement with the theoretical expectations.

Analysis of Partial Bias Schemes for the Writing of Crossbar Memory Arrays

Partial bias schemes reduce the disturbance during the writing of crossbar arrays (CBAs). Detailed analysis of two partial bias schemes is presented in this paper: 1) 1/2 bias scheme for low-power operation and 2) 1/3 bias scheme for high-performance (i.e., high $V_{\rm dd})$ operation. With partial bias schemes, a sneak leakage reversal phenomenon may occur due to line-resistance-induced voltage degradation, which provides a measure of voltage driving range along access lines. Voltage dividing effect of selector devices reduces disturbance in CBAs and leads to similar writing voltage margin in both bias schemes. Matching a proper partial bias scheme with the selector device choice optimizes the performance of CBAs.

A Sub-<inline-formula> <tex-math notation="LaTeX">${\boldsymbol kT}/\boldsymbol q$ </tex-math></inline-formula> Voltage Reference Operating at 150 mV

We propose a subthreshold CMOS voltage reference operating with a minimum supply voltage of only 150 mV, which is three times lower than the minimum value presently reported in the literature. The generated reference voltage is only 17.69 mV. This result has been achieved by introducing a temperature compensation technique that does not require the drain–source voltage of each MOSFET to be larger than $4 kT/q$ . The implemented solution consists in two transistors voltage reference with two MOSFETs of the same threshold-type and exploits the dependence of the threshold voltage on transistor size. Measurements performed over a large sample population of 60 chips from two separate batches show a standard deviation of only 0.29 mV. The mean variation of the reference voltage for $V_{\rm DD}$ ranging from 0.15 to 1.8 V is 359.5 $\mu $ V/V, whereas the mean variation of V $_{\rm {REF}}$ in the temperature range from 0 °C to 120 °C is 26.74 $\mu $ V/°C. The mean power consumption at 25 °C for $V_{\rm DD}= 0.15$ V is 26.1 pW. The occupied area is $1200~\mu $ m $^{2}$ .

An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi-<inline-formula> <tex-math notation="LaTeX">$\mathrm{V}_{\rm DD}$ </tex-math></inline-formula> CMOS/SIMOX Techniques

Many of the current wireline networks are digitalized. In Japan, a synchronous digital hierarchy (SDH) system is installed in the public switched telephone network, and application data are transferred with a synchronous transfer module (STM). This paper presents an STM-16 frame termination VLSI fabricated with a 0.3- $\mu $ m quintuple-metal CMOS/SIMOX process. To reduce power consumption, we employ a multi- $V_{\rm DD}$ architecture using 2- and 1-V power supplies. Also, fully depleted silicon on insulator (FD-SOI) devices are used to obtain a higher operating speed and to reduce dynamic power dissipation. To install another powerline in every standard cell without increasing the cell size, a stacked multiple powerlines scheme is proposed. In addition, some dedicated standard cells are developed to convert the logical high level without degrading the signal integrity. With regards to hard macros, 2-V MUX/DEMUX macros achieve a high operating speed of 2.5 Gb/s, while a dual-port SRAM macro can operate at a low supply voltage of 1 V. Moreover, 2-V 50- $\Omega $ -terminated input/output buffers using a new direct-drive amplifier operate without dedicated power supplies. With our STM-16 frame termination VLSI, the power consumption during the standby is 34 mW, and that for 2.5-Gb/s operation is 1.2 W at 25 °C.

A Small Signal Amplifier Based on Ionic Liquid Gated Black Phosphorous Field Effect Transistor

In this letter, we report an analog small signal amplifier based on semiconducting black phosphorus (BP), the most recent addition to the family of 2D crystals. The amplifier, consisting of a BP load resistor and a BP field-effect transistor (FET), was integrated on a single flake. The gain of the amplifier was found to be $\sim 9$ and it remained undistorted for input signal frequencies up to 15 kHz. In addition, we also report record high on current of 200 $\mu \text{A}/\mu \text{m}$ at $V_{\rm DD} =-0.5$ V in the BP FETs. Our results demonstrate the possibility for the implementation of BP in the future generations of analog devices.

Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called replacement spacer gate (RSG), is designed to avoid challenges in gate patterning and high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> metal gate filling. Planar bulk pMOSFETs, with SPW and halo doping, respectively, were simulated and fabricated adopting the RSG process. Due to its retrograde feature, the SPW can achieve low drain-induced barrier lowering (DIBL) along with low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula> . Compared with halo doping with the same <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{{T,{\rm sat}}}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\rm DD} = 0.8$ </tex-math></inline-formula> V, despite no <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{{\scriptscriptstyle ON}}}$ </tex-math></inline-formula> enhancement, the SPW reduces DIBL by 45% and enhances <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\rm EFF}$ </tex-math></inline-formula> by 18%. Compared with halo doping with the same <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{{\scriptscriptstyle OFF}}} = 100$ </tex-math></inline-formula> nA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\rm DD} = 0.8$ </tex-math></inline-formula> V, the SPW structure reduces DIBL by 16%, enhances <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{{\scriptscriptstyle ON}}}$ </tex-math></inline-formula> by 5%, and improves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\rm EFF}$ </tex-math></inline-formula> by 30%. In addition, with the self-aligned feature, the SPW does not deteriorate junction band-to-band tunneling (BTBT) leakage in comparison with halo doping. Otherwise, 20 times larger BTBT leakage will emerge due to the profile overlap between retrograde doping and drain/extension doping.

Ab-Initio Simulation of van der Waals MoTe2–SnS2 Heterotunneling FETs for Low-Power Electronics

Band-to-band tunneling field-effect transistors (TFETs) made of a vertical heterojunction of single-layer MoTe2 and SnS2 are investigated by means of 3-D, full-band, atomistic quantum-transport simulations relying on a first-principles basis. At a supply voltage ${V_{\rm dd}=0.4}$ V and OFF-current $I_{\mathrm{{\scriptscriptstyle OFF}}}=10^{-6}\mu \text{A} / \mu \text{m}$ , on-state currents $>75\boldsymbol {\mu }\text{A} / \boldsymbol {\mu }\text{m}$ are reported for both n- and p-type logic switches. Our findings indicate that metal-dichalcogenide heterojunction TFETs represent a viable option in low-power electronics.

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

Guided by the Wentzel-Kramers–Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and experimentally verified. Along this line, improvements achieved by the implementation of uniaxial strain in nanowires (NW), the benefits of high-k/metal gates, and newly engineered tunneling junctions as well as the effect of scaling the NW to diameters of 10 nm are demonstrated. Specifically, self-aligned ion implantation into the source/drain silicide and dopant segregation has been exploited to achieve steep tunneling junctions with less defects. The obtained devices deliver high on-currents, e.g., gate-all-around (GAA) NW p-TFETs with 10 nm diameter show ${I} _{\rm D} = 64~\mu $ A/ $\mu $ m at ${V} _{\rm DS} = {V} _{\rm GS} - {V} _{\rm off} = -1.0$ V, and good inverse subthreshold slopes (SS). Tri-gate TFETs reach minimum SS of 30 mV/dec. Dopant segregation helps to minimize the defect density in the junction and thus trap assisted tunneling (TAT) is reduced. Pulsed current-voltage (I-V) measurements have been used to investigate TAT. We could show that scaled NW devices with multigates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path enabled by the inherently good electrostatics. Furthermore, SiGe NW homo- and heterojunction TFETs have been investigated. The advantages of a SiGe/Si heterostructure as compared to a homojunction device are revealed and the effect of line tunneling which results in an increased BTBT generation is demonstrated. It is also shown that complementary strained Si TFET inverters and p-TFET NAND gates can be operated at ${V} _{\rm DD}$ as low as 0.2 V. This suggests a great potential of TFETs for ultralow power applications. The analysis of GAA NW TFETs for analog applications provided a high transconductance efficiency and large intrinsic gain, even higher than for state-of-the-art 20 nm FinFETs at low voltages.

Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells

We use mixed device-circuit simulations to predict the performance of 6T static RAM (SRAM) cells implemented with tunnel-FETs (TFETs). Idealized template devices are used to assess the impact of device unidirectionality, which is inherent to TFETs and identify the most promising configuration for the access transistors. The same template devices are used to investigate the $\text{V}_{\rm DD}$ range, where TFETs may be advantageous compared to conventional CMOS. The impact of device ambipolarity on SRAM operation is also analyzed. Realistic device templates extracted from experimental data of fabricated state-of-the-art silicon pTFET are then used to estimate the performance gap between the simulation of idealized TFETs and the best experimental implementations.

Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs

Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) poses a concern as to whether single-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> testing will suffice for low power nanometric designs. Our analysis shows multi-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> tests could be required, depending on the test speed. This knowledge can be exploited in small delay fault testing to reduce the chances of test escapes while minimizing cost.

A Systematic Design Methodology for Low-Power NoCs

Network-on-chip (NoC) communication architectures are emerging as the most scalable and efficient solution to handle on-chip communication challenges in the multicore era. In NoCs, power estimations in the early stages of the design help the designers to optimize the design for energy consumption and efficiently map applications to achieve low-power solutions. However, in 90-nm designs or below, the impact of parasitics not only influence timing closure, but also leads to variability in power and area budgets among different NoC architectures. There is a growing need for advanced design methodologies to overcome these issues in NoC designs. This paper presents a system-level design methodology based on layout and power models to achieve low-power and high-performance NoC designs. The impact of global interconnects with and without repeater insertion on the bandwidth and power is considered. Width and spacing of global interconnects and its effect on performance and power dissipation are analyzed. For architectural-level power analysis, different router designs for Chip-Level Integration of Communicating Heterogeneous Elements (CLICHE), Butterfly Fat Tree (BFT), Scalable, Programmable, Integrated Network (SPIN), and Octagon NoC architectures are implemented using ARMs 65-nm standard cell library in 65-nm Taiwan Semiconductor Manufacturing Corporation (TSMC) process. The router designs are synthesized in RVT process using a ${V}_{\rm dd}$ of 1.0 V and a temperature of 25$^{\circ}{\rm C}$ . Synopsys Prime Time-PX design tool is used for calculating average power dissipation of the router designs.

Soft-Error Performance Evaluation on Emerging Low Power Devices

Radiation-induced single-event upset (SEU) has become a key challenge for cloud computing. The proposed introduction of low bandgap materials (Ge, III-Vs) as channel replacement and steep switching devices for low-voltage applications may induce radiation reliability issues due to their low ionization energy and device architecture. In this paper, the soft-error generation and propagation in Si FinFET, III-V FinFET, and III-V Hetero-junction tunnel FET (HTFET) are investigated using device and circuit simulation. III-V FinFET shows enhanced charge collection compared with Si FinFET, whereas HTFET shows significant reduction of the bipolar gain effect and charge collection. Soft-error rate (SER) evaluation methodology has been proposed for these emerging devices based on the critical LET extraction. SRAM bit flip, electrical masking effect, and latching window masking effect have been analyzed with supply voltage scaling. The SER evaluation of SRAM and logic shows that HTFET-based circuits are promising for radiation resilient ultra-low power applications. III-V FinFET shows increased SER for SRAM for ${\rm V}_{\rm DD}$ range of 0.3–0.8 Vand reduced logic SER below 0.5 V compared with Si FinFET.

A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O Transceiver in 65 nm CMOS

A low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100–200 ${\rm mV}_{\rm ppd}$ using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range. In the transmitter clocking circuitry, per-phase duty-cycle and phase-spacing adjustment is implemented to allow adequate timing margins at low operating voltages. Fabricated in a general purpose 65 nm CMOS process, the transceiver achieves 4.8–8 Gb/s at 0.47–0.66 pJ/b energy efficiency for ${\rm V}_{\rm DD}=0.6$ –0.8 V.

Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits

This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$S.S.$</tex></formula> ) and comparable trap-induced <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{T}$</tex></formula> shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{\rm dd})$</tex></formula> , the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way nand, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\sim$</tex></formula> 24%–27% and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\sim$</tex></formula> 13%–15% variations in leakage and delay at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{ \rm dd} = \hbox{0.4}\ \hbox{V}$</tex></formula> , respectively, for the logic circuits evaluated.