Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations

Abstract

Interconnect opens are a major class of defects found in today’s nanometer technologies. These defects present subtle behavior that could lead to test escapes and hence compromise test quality. Furthermore, they could become a reliability risk. Low-voltage testing has been suggested as a static test to improve the defect coverage of interconnect opens. In nanometer technologies, process variability is predominant and considering only the nominal value of parameters is not realistic. Hence, process variations should be considered to analyze the behavior of interconnect opens. In this brief, the detection capabilities of low-voltage testing for interconnect opens considering process variations is investigated. A statistical model is used for the interconnect open defect. Correlation between parameters of the affected gates and spatial correlation of the parameters for those gates tied to the defective floating node have been considered. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS85 benchmark circuits. Based on these results, it is suggested to use low $V_{\rm DD}$ in conjunction with favorable logic conditions at the coupling lines to enhance the defect coverage of interconnect opens leading to better test quality and higher product reliability.