An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi-<inline-formula> <tex-math notation="LaTeX">$\mathrm{V}_{\rm DD}$ </tex-math></inline-formula> CMOS/SIMOX Techniques

Abstract

Many of the current wireline networks are digitalized. In Japan, a synchronous digital hierarchy (SDH) system is installed in the public switched telephone network, and application data are transferred with a synchronous transfer module (STM). This paper presents an STM-16 frame termination VLSI fabricated with a 0.3- $\mu $ m quintuple-metal CMOS/SIMOX process. To reduce power consumption, we employ a multi- $V_{\rm DD}$ architecture using 2- and 1-V power supplies. Also, fully depleted silicon on insulator (FD-SOI) devices are used to obtain a higher operating speed and to reduce dynamic power dissipation. To install another powerline in every standard cell without increasing the cell size, a stacked multiple powerlines scheme is proposed. In addition, some dedicated standard cells are developed to convert the logical high level without degrading the signal integrity. With regards to hard macros, 2-V MUX/DEMUX macros achieve a high operating speed of 2.5 Gb/s, while a dual-port SRAM macro can operate at a low supply voltage of 1 V. Moreover, 2-V 50- $\Omega $ -terminated input/output buffers using a new direct-drive amplifier operate without dedicated power supplies. With our STM-16 frame termination VLSI, the power consumption during the standby is 34 mW, and that for 2.5-Gb/s operation is 1.2 W at 25 °C.