Ripple Cancellation Research Articles

A Novel Approach to Ripple Cancellation for Low-Speed Direct-Drive Servo in Aerospace Applications

A Novel Approach to Ripple Cancellation for Low-Speed Direct-Drive Servo in Aerospace Applications

A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection

This paper presents a novel low dropout (LDO) regulator distinguished by its high power supply rejection (PSR) and low quiescent current. A capacitive feed-forward ripple cancellation (CFFRC) technique is introduced to effectively cancel power supply noise while simultaneously minimizing quiescent current. Additionally, the design incorporates feed-forward capacitors and back-to-back pseudo-resistors biasing to achieve reduced power consumption. Furthermore, the integration of negative feedback super source follower and Miller compensation techniques enhances the stability of the LDO. Fabricated using 180 nm CMOS technology, the LDO exhibits a quiescent current consumption of 20.4 μA. Experimental results demonstrate a maximal improvement of −41.55 dB in PSR compared to an LDO lacking these enhancements, with a maximum load current capability of 120 mA.

A new soft‐switching high step‐up DC–DC converter with low voltage stress

AbstractThis paper proposes a new high step‐up DC–DC converter with zero input current ripple for renewable energy sources applications, such as fuel cells. In this topology, a coupled inductor and a multiplier cell are used to achieve high voltage gains. The power switch in this proposed circuit turns on under zero voltage switching conditions. An active switch limits the maximum voltage stress across the main power switch. Moreover, all circuit diodes of the converter turn off without a reverse recovery problem. A detailed analysis of a high‐gain step‐up DC–DC converter is studied along with improved efficiency. The ripple cancellation of the input stage of the converter is done by adding an input inductor and capacitor. By including the parasitic elements, an approximate loss analysis was performed in PSIM and found the maximum efficiency of ∼96% in simulation and ∼94% in hardware for 200 W power level design for 30 V input voltage. Later on, the converter laboratory hardware prototype can be developed with selected parameters, and finally, experimental results have been used to validate the properties of the converter.

A Coupled L-LC Filter for Interleaved Buck Converter Ripple Cancellation

A Coupled <i>L-LC</i> Filter for Interleaved Buck Converter Ripple Cancellation

An Interleaved Current-Fed Integrated LLC Resonant Converter With Input Current Ripple Cancellation

An Interleaved Current-Fed Integrated LLC Resonant Converter With Input Current Ripple Cancellation

A High-PSRR NMOS LDO Regulator With Intrinsic Gain-Tracking Ripple Cancellation Technique

A High-PSRR NMOS LDO Regulator With Intrinsic Gain-Tracking Ripple Cancellation Technique

LIFETIME PREDICTION OF SINGLE-STAGE LED DRIVER CIRCUIT USING BAYESIAN BELIEF NETWORK

In light-emitting diode (LED) lighting, the driver commands the lifetime and the LED bulb. It is essential to predict the driver's lifetime during its design stage. This paper proposes a viable method to predict the lifetime of the LED driver based on its failure rate. A novel single-ended primary inductor converter (SEPIC) integrated parallel ripple cancellation circuit (PRC) topology of 30 W is considered to estimate the lifetime of the driver circuit. The failure rate model is regarded as a base to predict the lifetime of LED drivers using Bayesian belief network (BBN) analysis. The weakest links are the prime components to estimate the lifetime, and they are active devices and capacitors employed in the driver circuit. The output capacitor is considered a degree of importance as per the existing literature, and the proposed course has been designed without using any electrolytic capacitor (EC) to enhance the reliability of the driver circuit. This approach ensures an effective way to access the mean time to failure (MTTF) or the lifetime of the LED driver in a lucrative manner.

An E-Core Based Integrated Coupled Inductor for Interleaved Boost Converter

Interleaving in a boost converter is beneficial for lowering input and output current ripples through ripple cancellation due to phase-shift between channel currents. However, interleaving does not affect the channel current ripple. The channel current comprises circulating Differential Mode (DM) current and Common Mode (CM) boost current, whose ripples constitute the total channel current ripple. Inverse coupling between channel inductors effectively lowers channel current ripple while maintaining the same input and output current ripples. However, with a single inverse coupled inductor, its leakage inductance, which serves as a boost inductor, depends on the winding arrangement and is challenging to balance in both channels. To overcome this, the inverse coupled inductor can be implemented as a cascade of inverse (DM inductance) and direct (CM inductance) coupled inductors. The DM and CM currents and their ripples then depend on CM and DM inductances, respectively. Nonetheless, this approach results in increased size and count of magnetic cores. In this paper, an Integrated Magnetic Structure (IMS), based on a gapped EE-core, is proposed that combines both CM and DM inductances in a single core. The CM and DM inductances are independent and depend on separate winding turns. A reluctance model is derived, and a design procedure is developed where core parameters are expressed in terms of converter parameters. Finally, the proposed IMS concept is validated through a 300 W, 100 V to 168 V prototype, switching at 70 kHz.

An Equalization Current Ripple Cancellation (ECRC) Converter-Based Centralized Equalization System for Series-Connected Battery Strings

Battery equalization management is a key technology to ensure the high-performance and safe operation of electrified transportation such as electric vehicles and electric aircraft. In this paper, an equalization current ripple cancellation (ECRC) converter for centralized equalization system is presented. Compared with traditional methods, the ECRC converter-based equalization system achieves a zero-ripple equalization current, so that the unfavorable influence of larger current pulsation on battery cells is eliminated. Meanwhile, under a phase-shifted PWM modulation strategy, the ECRC converter not only implements zero-voltage switching (ZVS) of all switches to reduce switching loss, but also decreases the peak current of the transformer to reduce transformer loss, so that the efficiency of the equalization system is significantly improved. Besides, the value of each power element in the converter is comparatively small, which is conducive to improving the power density of the centralized equalization system. To confirm the theory analysis, an experimental prototype based on a battery string containing 13 cells is built for experimental verification, and a systematic comparison is implemented with existing centralized equalization methods. The experimental and comparison results verify the design of the proposed equalization system and reflect the obvious performance improvement over traditional methods.

Reduced Power Processing LED Driver With Constant Output Current

The performance of AC-DC LED drivers is determined by the power quality on both the AC and DC sides and the efficiency of the conversion. To satisfy these specifications, a dedicated LED driver is needed. Reduced power processing is the current trend for enhancing conversion efficiency without compromising power quality. LED drivers powered by single-phase AC must have a high power factor and low total harmonic distortion in order to maintain grid power quality. Constant current must be achieved by LED drivers in order to prevent flickering, which can cause health problems. This paper presents an architecture for driving LEDs that achieves a high power factor with reduced harmonics on the AC side and maintains flicker-free operation on the DC side. A unique ripple cancellation approach using split capacitors is proposed to achieve constant output current with high conversion efficiency while reducing redundant power processing and design complexity. The new architecture offers a simple control method for effective driver operation. The proposed driver can considerably reduce the energy storage requirement at 100 Hz. Experiments show that the proposed LED driver achieved a high power factor of 0.99 with lower input current harmonics and conversion efficiency of 94% at full power.

A Single-Switch Soft-Switched High Step-Down Zeta Converter With Low Output Current Ripple

This article proposes a new nonisolated high step-down converter that is derived from Zeta converter. By employing coupled-inductor technique, zero-current switching is achieved for the switch at turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> . Also, introduced converter incorporates a current ripple cancellation cell, which provides dc output current for full load as well as light load. Another main feature of the proposed converter is using a single switch and a magnetic core. Therefore, high efficiency and high power density are attained. For further efficiency improvement, a synchronous rectifier is employed, which results in efficiency greater than 96% for the entire load range. A 100-W prototype of the proposed converter is designed and implemented to verify the theoretical analysis and confirm its efficiency improvement and advantages.

GaN-based step-down power converter and control strategy for hydrogen energy systems

The conventional Si-based semiconductors suffer from low switching frequency, high conduction loss and low efficiency. These shortcomings hinder the improvement of power electronic power converter performance. An attractive solution is to replace Si-based semiconductor devices with the wide-bandgap semiconductors based on gallium-nitride material. In terms of the step-down converters which are used for hydrogen energy systems, it is difficult for the traditional buck circuit to eliminate the output current ripple and achieve fault-tolerant operation. Therefore, topologies of the step-down power converter also need improvement. In this paper, a GaN-based step-down power converter and control strategy for hydrogen energy systems is presented. Firstly, the mathematical analysis of the conventional buck converter is done to clarify why it has limitations regarding the reliability and current ripple. Another alternative solution is discussed but still suffers from ripples. In order to eliminate the current ripple and enhance the fault-tolerant ability, a novel GaN-based solution is given and both analysis and design are provided. The current ripple can be perfectly cancelled and fault-tolerant operation can be fully achieved. The comparison is carried out with the existing solutions. The time-domain simulation tests are carried out. And the experimental prototype is established based on the enhancement mode GaN transistor. The experimental results verify the effectiveness of proposed design regarding the current ripple cancellation and dynamic performance.

Electrolytic capacitor‐less reduced power processing single‐phase LED driver with power decoupling using split capacitor

SummaryLight emitting diode (LED) driver systems are now moving toward reduced processing power to improve conversion efficiency in indoor and outdoor applications. LED drivers connected to a single‐phase supply must meet the requirements for power factor correction with lower input current harmonics to maintain the alternating current (AC) power grid's quality and maintain a constant current through the LED load to eliminate the flickering effect in the light output. An LED driver is required to fulfill these requirements. In this paper, a new reduced processing power LED driver is proposed. By splitting the output capacitor into two capacitors and with the help of hardware design, the processing power can be reduced by using fewer semiconductors than in earlier designs. The proposed driver employs a simple ripple cancellation control approach to eliminate the 100 Hz ripple in the LED load current. Using this principle, an LED driver was designed and tested. The experimental results demonstrated that the proposed LED driver achieved an input power factor close to unity with lower input current harmonics and 92.5% of peak efficiency when operating at full power.

A combinable wireless power transfer design for extensible-capacity and adaptive charging of route UAVs with active ripple mitigation

This paper presents a combinable wireless power transfer (WPT) system for unmanned aerial vehicles (UAVs) with autonomous and adaptive charging of extensible capacity. By combining multiple transmission modules in parallel to power the UAV, the charging capacity of the system is dramatically enhanced and is adaptive to multiple power ratings with more flexibility. Meanwhile, the combination provides an approach for the system to improve reliability as each module can be operated independently. The mapping relationship between the transmitter (Tx) and the receiver (Rx) is investigated to estimate the amplitude and phase of output currents from the primary side. An active current ripple mitigation scheme based on real-time current estimation is proposed to regulate the Rx currents from the primary side and mitigate the synthetic current ripple without massive sensors onboard, by utilizing the interleaving technique, the output can achieve current ripple cancellation. And the experiment of a scaled-down prototype verifies that the output power of the combinable configuration is boosted up by 145.5% compared with that of a single module, meanwhile, the active ripple mitigation can indeed ameliorate the charging performance and prolong the battery life, the synthetic ripple amplitude is weakened remarkably by 79.06% whereas the efficiency is measured 5% higher than the system without ripple mitigation.

Single‐switch coupled‐inductors‐based high step‐up converter with reduced voltage stress

AbstractThis paper proposes a non‐isolated DC‐DC high step‐up converter. To achieve a high voltage conversion ratio and overcome the problems related to near unity duty‐cycle of the conventional boost converter in high step‐up applications, coupled‐inductors along with switch‐capacitor techniques are merged in this topology. The proposed converter provides continuous input current with low ripple without using any current ripple cancellation method and the voltage across the switch is limited inherently. In order to reduce the control circuit complexity, the proposed converter uses only one switch. These features decrease the complexity of the proposed converter structure. The voltage stress of the semiconductor components is reduced significantly; thus, high‐quality elements (fast power MOSFET switches with low on‐state resistance and Schottky diodes with low forward voltage drop along with low power losses) can be used, which minimizes the switching and conduction losses and improves the converter efficiency. To confirm the converter operation and theoretical analysis, a 200‐W prototype converter with 24‐to‐200‐V input and output voltages operating at 100‐kHz is implemented in the laboratory.

Fully Soft-Switched Non-Isolated High Step-Down DC–DC Converter With Reduced Voltage Stress and Expanding Capability

In this article, a fully soft-switched expandable high step-down dc–dc converter is presented. In order to achieve a high step-down voltage conversion ratio and low component count, the synchronous buck and Cuk converters are integrated. Lower switches’ voltage stress is realized by splitting the input voltage, which can considerably decrease the switches’ conduction loss. Moreover, switching losses along with the reverse recovery problems are mitigated due to the soft-switching operation of all semiconductor devices. The switch utilized for soft-switching operation is also used to replace the output diode as a synchronous rectifier, which reduces the conduction loss. The mentioned features have considerably contributed to the converter efficiency. Furthermore, the converter shares a common ground between the input and the output, which is desirable in many applications, while the converter output current is continuous without adding current ripple cancellation methods. Finally, the number of converter cells can be expanded or reduced; therefore, the converter can be applied to a wide range of loads. The operating principles and analysis of the proposed converter are presented, and the results from the implemented prototype are provided to verify the converter operation and performance.

Novel Soft-Switched Three-Phase Inverter With Output Current Ripple Cancellation

A novel three-phase dc–ac full-bridge soft-switched inverter topology is proposed in this article that provides an ultralow ripple output current. The proposed circuit utilizes a passive filter that comprises a transformer, an inductor, and a capacitor for achieving soft switching and output current ripple cancellation. Zero-voltage switching (ZVS) is achieved at turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> time instant for all the switches in the proposed circuit. The magnitude of ZVS current is optimized throughout the line cycle by the application of the variable frequency modulation technique. In addition to soft switching, an ultralow ripple output current is achieved due to the current ripple cancellation property of the proposed circuit. The output current ripple cancellation is achieved by combining the inverter current with an additional high-frequency ripple current generated by the passive filter. The soft-switched inverter operation and inherent current ripple cancellation achieved by the proposed circuit, result in a high power conversion efficiency. Theoretical analysis and the improvements in inverter performance presented in this article are validated through the experimental verification of the proposed converter topology using a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf{600\text{-}W}$</tex-math></inline-formula> lab prototype.

A Practical Digital Implementation of Completely Decentralized Ripple Minimization in Parallel-Connected DC–DC Converters

Parallel dc–dc converters are commonplace in applications such as computing power supplies, point of load systems, and dc microgrids. The presence of multiple converters in such systems allows for switch interleaving and ripple cancellation. One class of existing ripple reduction methods depends on central controllers that require communication among the converters. These approaches compromise system scalability and reliability. When it comes to decentralized methods, the state-of-the-art is limited to uniform conditions and cannot handle mismatches in physical parameters and operating points among converters. In this article, we address these shortcomings with fully decentralized controller that robustly drives the pulsewidth modulation carriers of a collection of heterogeneous converters to the phase-shifts that give minimized ripple. More precisely, the proposed controller eliminates the dominant fundamental switching harmonic from the output current and voltage using only local voltage feedback. After outlining a comprehensive analytical model, we experimentally validate our approach on a system of five parallel-connected buck converters under a variety of parametric and operational mismatches. Measurements show ripple reduction of more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$4\times$</tex-math></inline-formula> in the output voltage and the fundamental switching frequency harmonic is attenuated by more than 30 dB compared to conventional symmetric interleaving.

Ripple-Free Multiphase Interleaved Stacked Converter for High-Power Applications

A novel control technique that guarantees a ripple-free output current and voltage of a dc–dc multiphase staked interleaved converter is proposed. The conventional multiphase interleaved converters have been extensively used in various applications. However, ripple cancellation in these converters solely depends on the number of phases and can only be achieved at specific duty cycles. On the other hand, wide-range and ripple-free output are important paramount features for many modern applications. Therefore, the presented converter aims to combine the advantages of both the multiphase interleaved and the stacked converters into a single-unit converter suitable for high-power applications. Ripple-free output current/voltage is always guaranteed regardless of the number of phases and duty cycle values. This feature is accomplished by adding a fractionally-rated phase-leg to the conventional multiphase interleaved converter and modulating it with the proposed control approach. The configurable logic block, a state-of-the-art tool developed by Texas Instruments, is utilized to reduce the hardware size of the entire conversion system while increasing its speed and flexibility. Extensive simulation studies are carried out to confirm the functionality of the proposed control scheme. A laboratory porotype is developed to validate the effectiveness of the proposed control method experimentally. With only a few more components, significant reductions in output ripples are achieved.

A 0.9-μA Quiescent Current High PSRR Low Dropout Regulator Using a Capacitive Feed-Forward Ripple Cancellation Technique

This article presents a high power supply rejection ratio (PSRR) low dropout (LDO) regulator with a low quiescent current. A low quiescent current capacitive feed-forward ripple cancellation (CFFRC) technique is proposed to cancel the power supply noise. With this technique, low power consumption is achieved via feed-forward capacitors and back-to-back pseudo-resistors bias. This design was fabricated using the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. The entire proposed LDO consumes a quiescent current of 0.9 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> . Compared with an LDO without enhancement, at the maximum load current of 200 mA, the measured PSRR has an enhancement of −22 dB at 1 MHz.