Ripple Cancellation Research Articles

A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">including</i> on-chip reference buffers.

Analysis, design, and minimum phase selection of high power interleaved DC–DC converter

SummaryThe primary use of interleaved bidirectional DC–DC converters (IBC) is for high current applications due to the inherent property of ripple cancellation, high redundancy, and improved efficiency. Proper analysis and design are required to improve the power density and reduce the cost of the ‐phase IBC. Ripple current analysis plays a vital role in choosing the inductor and filter capacitors to minimize the size of an IBC. This paper presents the simple and generalized formulas for the current ripple minimization of ‐phase IBC. Also, the inductor is designed with two different core materials, namely, Ferrite and Sendust. It is observed that the area product and weight of the magnetics have been reduced by 22% and 23%, respectively, for Sendust core in comparison with the Ferrite core. Furthermore, a discussion regarding the thermal analysis of IGBT modules to select an appropriate heat sink is stated. Moreover, the minimum phase selection has been proposed by considering several constraints such as area product of the core, discrete components size based on ripple analysis, cost of all components, and converter efficiency. The prototype of the selected minimum phase IBC has been developed and tested for a 7.5 kW power level using TMS320F28335.

A high PSR LDO with adaptive loop switching control and feedforward ripple cancellation techniques

This paper proposed a low-dropout regulator (LDO) with adaptive loop switching control (ALSC) and high-pass filter-based feedforward ripple cancellation (HPFRC) techniques. The ALSC circuit can be utilized for wide-input-range LDO and provide a clean power supply for the bandgap reference (BGR) without a pre-regulator circuit. The power supply rejection (PSR) at low frequencies of the proposed LDO is insensitive to the limited PSR of BGR. In addition, the HPFRC circuit can enhance the mid-range PSR of the LDO. This circuit has been designed and verified in 0.25-μm BCD technology. The simulation results demonstrate that the output voltage of 5 V is stable with a 2.2 μF output capacitor when an input voltage from 5.25 V to 24 V is applied. The LDO consumes only 36.4 μA at full load, and the line and load regulation are simulated as 0.02 mV/V and 9.2 μV/mA, respectively. It achieves a PSR of –72 dB at 1 MHz for heavy loads.

Reliability analysis of flicker-free LED driver based on five-level rectifier

LEDs are powered by LED drivers, and the output of these drivers determines how well an LED performs. As a result, in the lighting industry, low-cost, flicker-free output profile, better efficiency, and maintaining unity power factor (UPF) operation during the AC to DC conversion are highly appreciated. Although traditional LED rectification systems are inexpensive and straightforward, they distort the grid current and inject harmonics into it. In this context, this study provides a sensor-free self-balanced multilevel rectifier (MLR) topology that can drive the LED while preserving UPF under all operational circumstances. To counteract the stroboscopic effect generated by current ripples supplied to LEDs, this study implements a ripple cancellation (RC) system. This RC approach also provides a regulated DC supply, minimizes the smoothing capacitor size, and provides decoupled single loop current control. Further, a rigorous reliability investigation of the complete system carried out over a 20-year period. The proposed system has been validated through experimentation on the laboratory-developed prototype and the relevant results are reported in terms of controller performance, MLR and RC waveform.

Transfer Function Analysis of the Power Supply Rejection Ratio of Low-Dropout Regulators and the Feed-Forward Ripple Cancellation Scheme

This paper presents a rigorous transfer function analysis of the power supply rejection ratio (PSRR) of low-dropout (LDO) regulators and the LDO with the feed-forward ripple cancellation (FFRC) scheme. Four main noise sources of conventional LDOs are first clarified. An efficient and accurate model is proposed to facilitate the analysis, and the transfer function, along with the poles and zeros, is derived based on the simplified model. Software simulation results and numerical plots are both demonstrated and compared to verify the analytical results, with respect to two specific design examples. The widely-used FFRC scheme for PSRR enhancement is also reinvestigated based on the proposed model. With the inclusion of the FFRC circuit, the new transfer function with new poles and zeros is presented. The working principles of the FFRC scheme are illustrated and the optimal FFRC case is clarified. The proposed model and the derived transfer function match well with the simulation results and the measurement results in prior works. The proposed model and the analytical results serve as the theoretical foundation of the design of high-PSRR LDOs. The recommended simulation methodology could be helpful during the circuit design phase.

High step-up-coupled inductor SEPIC DC–DC converter with input current ripple cancellation

High step-up-coupled inductor SEPIC DC–DC converter with input current ripple cancellation

Torque Ripple Minimization Control Strategy in Synchronous Reluctance Machines

Torque smoothness is an essential requirement for high-performance motor drive applications. Synchronous reluctance machines (SyRM) have high torque ripple due to non-linear magnetic circuit and saturation. Typically, in Permanent magnet machines the active torque ripple compensation is achieved by injecting a compensating ripple current in the <i>q-axis</i>. For SyRM, the current injection method for active torque ripple cancellation can be used in both the <i>d-axis</i> and <i>q-axis</i>. However, the saturation of the motor parameters with the changing current can result in varied performance between the two methods. This paper evaluates the effectiveness of both of these methods for torque ripple cancellation. For evaluation, the impact of parameter saturation with ripple current injection on the <i>d-axis</i> and the <i>q-axis</i> is studied. The mathematical conclusions obtained are evaluated by both the simulation and the experimental results performed on a 4 pole 1200W Synchronous reluctance machine.

Conducted emission simulation and measurement of interleaved DC-DC converters

Switching-Mode Power Supplies (SMPS) are often used to power on-board satellite payloads due to their good conversion efficiency. However, they emit radiated and conducted noise, which can disturb the operation of other payloads. The current ripple sum of the power supplies will appear on the power bus. There are many methods to reduce this summarized noise, one of them is to interleave the on-switching times of the converters. This ripple cancellation method can decrease the noise component on the switching frequency and on its upper harmonics. In this article we are going to demonstrate the effects of the distributed interleaving with a measurement platform consisting of two Pulse Width Modulation (PWM) controlled Buck controllers.

Design and Implementation of Single Stage SEPIC Integrated Parallel Ripple Cancellation Method for LED Lighting

Design and Implementation of Single Stage SEPIC Integrated Parallel Ripple Cancellation Method for LED Lighting

Fast‐converging robust PR‐P controller designed by using symmetrical pole placement method for current control of interleaved buck converter‐based PV emulator

AbstractIn this study, the interleaved buck converter‐based photovoltaic (PV) emulator current control is presented. A proportional‐resonant‐proportional (PR‐P) controller is designed to resolve the drawbacks of conventional PI controllers in terms of phase management, which means balancing currents evenly between active phases to avoid thermally stressing and provide optimal ripple cancelation in the presence of parameter uncertainties. The resonant path of the controller (PR) with a constant proportional unity gain is designed considering the changing dynamics of a notch filter by pole placement method (adding mutually complementary poles to the notch transfer function) at PWM switching frequency. The proportional gain path (P) of the controller is used to determine the compatibility of the controller with parameter uncertainty of the phases and designed by utilizing loop‐shaping method. The proposed controller shows superior performance in terms of 10 times faster‐converging transient response, zero steady‐state error with significant reduction in current ripple. Equal load sharing that constitutes the primary concern in multiphase converters is achieved with the proposed controller. Implementing of robust control theory involving comprehensive time and frequency domain analysis reveals 13% improvement in the robust stability margin and 12‐degree bigger phase toleration with the PR‐P controller. In addition to these, the proposed unconventional design process of the controller reduces the computational complexity and provides cost‐effectiveness and simple implementation. Moreover, implementing of auxiliary resistor‐capacitor (RC) circuits parallel with the inductors to sense the current in each phase removes the need for current measurement sensors that contribute to overall cost of the system.

A Novel Ultrafast Transient Constant on-Time Buck Converter for Multiphase Operation

Constant on-time control (COT) has been widely adopted in buck converters because of its simplicity, fast transient response, and high light-load efficiency. However, the increasing power demands of CPUs and AI/ML engines is pushing voltage regulators to support higher output currents, which typically requires the use of multiphase operation. However, since most high-performance COT schemes utilize ripple as a control variable, the ripple cancellation point in multiphase designs imposes difficult stability concerns, limiting performance, and robustness. In this article, a novel ultrafast transient COT (UFTCOT) control scheme is proposed to enable fast and robust operation even in multiphase converters. The small-signal models of the proposed control scheme are derived based on a describing function technique, whose theoretical results are compared, along with simulation and measurement results, to contrast the proposed UFTCOT technique to exiting approaches.

Differential Evolution Based Algorithm for Optimal Current Ripple Cancelation in an Unequal Interleaved Power Converter

This paper proposes an optimal methodology based on the Differential Evolution algorithm for obtaining the set of duty cycles of a recently proposed power electronics converter with input current ripple cancelation capability. The converter understudy was recently introduced to the state-of-the-art as the interleaved connection of two unequal converters to achieve low input current ripple. A latter contribution proposed a so-called proportional strategy. The strategy can be described as the equations to relate the duty cycles of the unequal power stages. This article proposes a third switching strategy that provides a lower input current ripple than the proportional strategy. This is made by considering duty cycles independently of each other instead of proportionally. The proposed method uses the Differential Evolution algorithm to determine the optimal switching pattern that allows high quality at the input current side, given the reactive components, the switching frequency, and power levels. The mathematical model of the converter is analyzed, and thus, the decision variables and the optimization problem are well set. The proposed methodology is validated through numerical experimentation, which shows that the proposed method achieves lower input current ripples than the proportional strategy.

Maximizing Ripple Cancellation in Input Current for SIDO Boost Converter by Design of Coupled Inductors

The requirement of multiple voltage levels in various applications has necessitated the development of single-input dual-output (SIDO) converters. This article focuses on a magnetically coupled-inductor SIDO (CI-SIDO) boost converter. In any converter, ripples in input current need to be reduced to decrease the requirements of input filters, to meet the strict restrictions on input current ripples, and several other benefits. In converters such as interleaved boost converters, maximum ripple cancellations are introduced to reduce the ripples in input current by shifting gate pulses. However, unlike an interleaved boost converter, the CI-SIDO boost converter has two unequal inductances and two different output voltages. In addition to the shifting of gate pulses, the maximum ripple cancellation in the CI-SIDO boost converter depends on the design of coupled inductors. This article analyzes the effect of coupled inductors on the maximum ripple cancellation and proposes a design for coupled inductors to achieve the maximum ripple cancellation. The proposed design method is explained and verified using practical examples. The findings of the analysis are verified experimentally by the laboratory prototype.

A flicker-free decoupled ripple cancellation technique for LED driver circuits

Light-emitting diode (LEDs) even though are the major lighting source, they suffer from flickering which has adverse effects on human health. With this wide increase in usage, more focus has been on minimizing the ripples, which is the root cause of flickers in LED driver circuits. Initial solution of electrolytic capacitor suffers from shorter lifetime, bulky weight, and high risk of fault. In this regard, a series current ripple cancellation (RC) technique has been proposed in this paper for flicker free operation. The key features of the proposed RC method include unity power factor (UPF) at source end, simple control, and reduced smoothing capacitance value. The proposed system has been validated in both MATLAB/Simulink environment and experimental investigations. Further, detailed analysis and comparative evaluation with the state-of-the-art work reported in the literature has been presented.

Interleaved Single-Stage LLC Converter Design Utilizing Half- and Full-Bridge Configurations for Wide Voltage Transfer Ratio Applications

Automotive on-board dc-dc converters are required to operate over a wide input and output voltage range depending on the state of charge of the input and the output battery. Conventionally, the unidirectional power transfer between these batteries is enabled by a two-stage converter concept. A first-stage nonisolated dc-dc converter regulates the input voltage of the galvanically isolated second-stage dc-dc converter such that the second-stage converter operates in its optimum operating point. This article presents a single-stage interleaved LLC resonant converter of 3.6 kW for this purpose. While LLC converters are usually not suitable to cover such a wide voltage range (the input voltage between 240 and 420 V and the output voltage between 8 and 16 V), this LLC converter is operated in a full-bridge mode for large gains and in a half-bridge mode for low gains. For intermediate gains and loads, the LLC employs the phase-shift mode. To operate the interleaved LLCs at equal switching frequencies enabling output current ripple cancellation to reduce the output capacitor, again, the phase-shift mode is utilized to balance the power transfer during the full-bridge mode while the asymmetrical duty-cycle mode is proposed for power balancing during the half-bridge mode. This article analyzes the converter design for these modes of operation and provides a comprehensive design procedure allowing the designer to simultaneously analyze all stress values for various resonant tank designs. A 3.6-kW prototype employing Si superjunction MOSFETs achieves a power density of 2.1 kW/L. The maximum efficiency reaches 96.5%, while for most operating points, it is kept well above 90%. The experimental measurement results validate the analysis and show that phase-shift operation and asymmetrical duty-cycle modulation can be utilized for power balancing for full-bridge and half-bridge configurations, respectively, such that a much smaller output capacitor can be employed.

High-PSRR Low-dropout Regulator with Fast Transient Response Time and Low Output Peak Voltage

This study proposes the feed-forward ripple cancellation (FFRC) technique to low drop-out (LDO) regulator. By adding load tracking impedance to the gate of pass transistor, it is possible to secure stability with a 100-nF capacitor having low ESR and be obtained less than 35 ㎱ response time. In all frequency bands, a power supply rejection ratio (PSRR) less than -70 ㏈ is obtained when the load current is 10 ㎃. The circuit is implemented in 65-㎚ CMOS process.

DC-Link Current Harmonic Mitigation via Phase-Shifting of Carrier Waves in Paralleled Inverter Systems

DC-connected parallel inverter systems are gaining popularity in industrial applications. However, such parallel systems generate excess current ripple (harmonics) at the DC-link due to harmonic interactions between the inverters in addition to the harmonics from the PWM switching. These DC-link harmonics cause the failure of fragile components such as DC-link capacitors. This paper proposes an interleaving scheme to minimize the current harmonics induced in the DC-link of such a system. First, the optimal phase-shift angle for the carrier signal is investigated using the analytical equations, which provides maximum capacitor current ripple cancellation (i.e., at the main switching frequency harmonic component). These optimally phase-shifted switching cycles lead to variations of the output current ripples, which, when summed together at the DC-link, result in the cancellations of the DC-link current ripples. The results show that when the carrier waves of the two inverters are phase-shifted by a 90° angle, the maximum high-frequency harmonic ripple cancellation occurs, which reduces the overall root-mean-square (RMS) value of the DC-capacitor current by almost 50%. The outcome of this proposed solution is a cost-effective DC-harmonics mitigating strategy for the industrial designers to practically configure multi-inverter systems, even when most of the drives are not operating at rated power levels. The experimental and simulation results presented in this paper verify the effectiveness of the proposed carrier-based phase-shifting scheme for two different configurations of common DC connected multi-converter systems.

Torque Ripple Reduction Method in a Multiphase PM Machine for No-Fault and Open-Circuit Fault-Tolerant Conditions

This paper presents a method that has been developed to reduce the torque ripples under healthy and open-circuit fault-tolerant (OCFT) conditions for a multiphase permanent magnet (PM) machine. For smooth torque, both the phase current and the back electromotive force (back-EMF) should be purely sinusoidal. To improve the torque in a multiphase machine, higher-order current harmonics are injected, which are related to the harmonics in the back-EMF. For this reason, generally, multiphase machines are designed with higher-order back-EMF harmonics. However, these harmonics produce ripples in the torque. In light of this, a torque ripple cancellation method has been developed that first determines an additional current component from the harmonic content of the back-EMF and then injects these additional components to cancel the torque ripple. It has been found that this new torque ripple cancellation method works for both faultless and faulty conditions in a five-phase PM machine. The method has been validated using Finite Element Analysis, and the results are presented in this paper.

Power Factor Preregulation in Interleaved Luo Converter-Fed Electric Vehicle Battery Charger

This work deals with the design and implementation of a new interleaved Luo power factor preregulator (PFP)-based electric vehicle (EV) battery charger, which is suitable for low-cost and improved power quality (PQ)-based EV charging. By interleaving two Luo converter cells, the input current is divided between them, which provides reliable and efficient charging of the battery at high-power discontinuous conduction mode (DCM) operation. This reduces the switch conduction loss due to reduced device current stress and thus, the charger efficiency is improved. The interleaved Luo converter incorporates low input and output current ripple due to ripple cancellation. This charger operates in constant current mode up to certain battery state of charge (SOC). However, for higher SOC range, it maintains constant voltage charging using a flyback converter at the next stage. Two converters are designed in DCM to provide inbuilt zero current switching and circuit diodes show good reverse recovery. An inherent PF preregulation is obtained at input mains over a wide range of supply voltages as well as dc-link voltage. The total harmonic distortion of input current is obtained as per PQ regulations. Its prototype is built and tested to validate its improved performance over two-stage solutions.

MOS capacitor based Dickson charge pump and ripple cancellation techniques using an LC circuit

This paper proposes a new architecture using integrated inductor and MOS capacitor based on Dickson charge pump associated with two parallel LC circuit after the first stage and output stage which cancel the ripple voltage that is generated in the output stage. In this circuit, the MOS capacitor as used instead of pumping capacitor, which helps in reducing the circuit Silicon area. Efficiency up to 80–90% can be achieved by reducing the parasitic effects and by using a MOS capacitor. The efficiency conversion and voltage gain increase or decreases depending on inductor and capacitor values. Vt drop loss is managed using high voltage clock. It shows that 3.5 V output voltage is generated from input voltage of 1.0 V with five stages of MOS capacitor (used as Pumping capacitor) in working frequency of 100 MHz the simulations were performed in Cadence Virtuoso platform with 0.18 μm CMOS process.