Ring Oscillator Physical Unclonable Functions Research Articles

Analysis the performance of Delay Locked Loop Physically Unclonable Functions for smart energy meter

The provision of secure and sustainable energy services is ensured by this research, also contributing to the advancement of technology align with the Sustainable Development Goals (SDGs). The motivation behind this study stems from the critical need to bolster hardware security within cutting-edge smart grid infrastructure, and more specifically, for smart energy metering technology. To address this need, this paper introduces a feasible and modular approach for enhancing the security through the implementation of a cryptographic key generator. This key generator is based on a modified Delay-based Physically Unclonable Function (PUF), which incorporates the innovative concept of a Delay Locked Loop(DLL).The reliability of the proposed PUFs has been rigorously assessed, demonstrating impressive performance levels of 98.02% and 99.1% across a wide temperature and supply voltage, spanning from -40°C to 80°C and (3.0-3.6) V. This is showcasing exceptional functionality within the smart meter’s operational parameters.The effectiveness of this approach is confirmed through practical testing conducted on the ZYNQ-7 ZC 702 Field-Programmable Gate Array (FPGA) platform.The outcomes are encouraging by substantial uniqueness (55.96% and 56.2%) and uniformity (51.2% and 49.15%). This research significantly advances the state of the art by surpassing previous investigations into XOR Arbiter PUF (XOR APUF) and Configurable Ring Oscillator PUF (CRO PUF) designs. Furthermore, the paper delves into an examination of the proposed design’s resilience against modeling attacks, along with comprehensive security assessments.

A dependable and resource-frugal ring oscillator physically unclonable function

ABSTRACT Silicon Physical Unclonable Function (PUF) is a crucial component for hardware security, providing unique device identification in networks. PUF provides robust security for cryptographic keys and IC digital fingerprints. However, resource constraints in network devices limit its use in security protocols. To address this challenge, PUF offers a lightweight hardware security solution with two main types: strong PUF (e.g. arbiter PUF) and Ring Oscillator (RO) PUF. The first option produces large CRPs with improved security but incurs hardware overhead, whereas the second option offers lower overhead with smaller CRP size, leading to reduced security. This paper introduces a novel, cost-effective solution to enhance RO PUF security while reducing hardware limitations. Our proposal involves a resource sharing technique with scan flip-flops, multiplexers, and inverter logic. This approach takes advantage of existing scan chains in circuit netlists to reduce PUF area without sacrificing uniqueness. A specific set of test patterns and odd number of inverters transform the memory-based PUF into an RO PUF. Our solution also leverages pass transistor-based implementation to significantly reduce power consumption and area overhead. Simulation results show that our approach effectively reduces area and power consumption while maintaining PUF uniqueness.

Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement

Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement

A novel low hardware configurable ring oscillator (CRO) PUF for lightweight security applications

Physical unclonable function (PUF) is a promising hardware security primitive that can generate a unique secret key peculiar to each chip by extracting the differences of non-reproducible manufacturing variations for the same implementations. Although there are several types of PUF designs and structures, ring oscillator (RO) PUF is one of the most prominent PUFs due to its straightforward implementation and remarkable performance. However, the traditional RO-PUF does not support large sizes of input/output combinations or challenge-response pairs (CRPs), as it is called in the scope of PUFs. Consequently, RO-PUF is more vulnerable to adversary attacks which can reveal the PUFs’ CRPs using a machine learning approach. Increasing the size of RO-PUF's CRPs requires a high increase in the circuit size leading to unacceptable area overhead for lightweight applications. The primary technique used to increase RO-PUF CRPs’ size without increasing the size of the required hardware is to develop a configurable ring oscillator (CRO) PUF. In this paper, we propose a configurable logic unit (CLU) that can be utilized to build a low-hardware CRO-PUF. The proposed CLU consists of a 1-XOR gate and a 1-XNOR gate. Building a CRO-PUF using the proposed CLU dramatically increases the CRPs size while minimizing the required hardware. The proposed CRO-PUF achieves excellent evaluation results, with measured uniqueness of 50.1 %, uniformity of 49.45 %, and reliability of 98.33 %. These values are in close proximity to the ideal targets of 50 % for uniqueness and uniformity, and 100 % for reliability

Reliability analysis and comparison of ring-PUF based on probabilistic models

—To address the issue of maladaptive reliability theory models in delay-based physical unclonable functions (PUF) of ring classes, this paper begins by analyzing the relationship between four key transistor parameters (channel length, channel width, threshold voltage, and gate oxide thickness) and delay sensitivity. Then establishes reliability quantification formulas for various PUF types, including ring oscillator PUF, k-out-of-1 PUF, Loop PUF, transient effect ring oscillator PUF, and duty cycle PUF. This analysis and comparison are conducted using the inverter delay model and probabilistic statistical methods to ensure fairness at the theoretical level. Finally, the proposed model is validated through simulation experiments, along with further analysis and comparison of ring-PUF. The results demonstrate that delay sensitivity can be utilized to assess the extent of delay impact when process parameters fluctuate. In terms of reliability, the ring-PUF can be ranked as follows: k-out-of-1 PUF, Loop PUF, ring oscillator PUF, transient effect ring oscillator PUF, and duty cycle PUF. This paper offers extensive technical guidance and theoretical support for ring PUF designers.

Integrating Lorenz Hyperchaotic Encryption with Ring Oscillator Physically Unclonable Functions (RO-PUFs) for High-Throughput Internet of Things (IoT) Applications

With the combined call for increased network throughput and security comes the need for high-bandwidth, unconditionally secure systems. Through the combination of true random number generators (TRNGs) for unique seed values, and four-dimensional Lorenz hyperchaotic systems implemented on a Stratix 10 Intel FPGA, we are able to implement 60 MB/s encryption/decryption schemes with 0% data loss on an unconditionally secure system with the NIST standard using less than 400 mW. Further, the TRNG implementation allows for unique encryption outputs for similar images while still enabling proper decryption. Histogram and adjacent pixel analysis on sample images demonstrate that without the key, it is not possible to extract the plain text from the encrypted image. This encryption scheme was implemented via PCIe for testing and analysis.

An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA

The ring oscillator (RO) PUF can be implemented on different FPGA platforms with high uniqueness and reliability. To decrease the hardware cost of conventional RO PUFs, a new design using the programmable delay units is proposed, namely, PRO PUF. The programmable interconnect points (PIPs) of programmable delay units are used to enhance the configurability. The PUF cell of the proposed design has the ability to be efficiently programmed to an RO PUF at any stage by adjusting the propagation paths of the delay units. A significant number of responses can be generated by the proposed PRO PUF while consuming fewer hardware resources. To verify the performance, the proposed design has been implemented on Xilinx FPGAs and also simulated using a standard 40nm technology. The experimental results have shown that the proposed design achieves high uniqueness, reliability, and hardware efficiency. Moreover, the PRO PUF has been evaluated using a machine learning attack, the CMA-ES attack. The results have shown that the proposed structure is more resistant to common modeling attacks when compared to conventional RO-related PUF designs.

A robust architecture of ring oscillator PUF: Enhancing cryptographic security with configurability

Physically Unclonable Functions (PUFs) are becoming more widely recognized as tamper-resistant, high-entropy hardware security primitives. Leveraging the intrinsic manufacturing properties of integrated circuits, PUFs provide a lightweight, cost-effective technique for device identification and cryptographic key generation. Despite the existence of various PUF designs and architectures, the ring oscillator (RO) PUF stands out as one of the most notable. This significance is due to its simplicity of implementation and outstanding performance metrics. However, traditional RO-PUFs are often classified as weak PUFs because they support a limited size of input-output combinations. This paper introduces a configurable inversion unit designed to construct a lightweight, robust architecture configurable (RAC) RO-PUF. The proposed unit comprises an XOR gate, an XNOR gate, and a multiplexer. The RACRO-PUF significantly increases the size of generated output bits while efficiently utilizing minimal hardware resources. The performance of the RACRO-PUF stands out in evaluations, recording a uniqueness of 49.78 %, uniformity of 49.42 %, reliability of 97.72 %, and impressive randomness of 98.34 %.

A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations

The physical unclonable function (PUF) is a hardware security primitive that can be used to prevent malicious attacks aimed at obtaining device information at the hardware level. The ring oscillator (RO) PUF has attracted considerable research attention. To improve the reliability of the RO PUF under voltage and temperature changes, the response of the duty-cycle (DC) PUF was obtained by comparing the duty cycle of the RO rather than the period. However, this method reduces the effective utilization of process variations, which limits its implementation in mature advanced manufacturing processes. In this study, a splitting duty-cycle (SDC) PUF was proposed to balance the effective extraction of process variations and robustness under voltage and temperature changes. The sensibility formula between the performance of SDC PUF and process, voltage, and temperature was established through a circuit model and statistical methodology, and the comprehensive characteristics of SDC PUF were analyzed theoretically. Next, 16 SDC PUFs with 128-bit responses were implemented and measured on a Xilinx Virtex-7 device. The experimental results revealed that the average native reliability of SDC PUF was 98.97%, and the reliability was 97.32% under various voltage and temperature conditions. This result revealed advantages over the DC PUF implemented in the same device. The uniqueness of the SDC PUF was 50.42%, and it passed the NIST SP 800-22 randomness and autocorrelation function tests.

FOM-CDS PUF: A Novel Configurable Dual State Strong PUF Based on Feedback Obfuscation Mechanism against Modeling Attacks

The configurable Ring oscillator Physical unclonable function (CRO PUF) is the newly proposed strong PUF based on classic RO PUF, which can generate exponential Challenge-Response Pairs (CRPs) and has good uniqueness and reliability. However, existing proposals have low hardware utilization and vulnerability to modeling attacks. In this paper, we propose a Novel Configurable Dual State (CDS) PUF with lower overhead and higher resistance to modeling attacks. This structure can be flexibly transformed into RO PUF and TERO PUF in the same topology according to the parity of the Hamming Weight (HW) of the challenge, which can achieve 100% utilization of the inverters and improve the efficiency of hardware utilization. A feedback obfuscation mechanism (FOM) is also proposed, which uses the stable count value of the ring oscillator in the PUF as the updated mask to confuse and hide the original challenge, significantly improving the effect of resisting modeling attacks. The proposed FOM-CDS PUF is analyzed by building a mathematical model and finally implemented on Xilinx Artix-7 FPGA, the test results show that the FOM-CDS PUF can effectively resist several popular modeling attack methods and the prediction accuracy is below 60%. Meanwhile it shows that the FOM-CDS PUF has good performance with uniformity, Bit Error Rate at different temperatures, Bit Error Rate at different voltages and uniqueness of 53.68%, 7.91%, 5.64% and 50.33% respectively.

Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version

We study a new transistor-level side-channel leakage caused by charges trapped in between stacked transistors namely residual electric charges (RECs). Building leakage models is important in designing countermeasures against side-channel attacks (SCAs). The conventional work showed that even a transistor-level leakage is measurable with a local electromagnetic measurement. One example is the current-path leak [1], [2]: an attacker can distinguish the number of transistors in the current path activated during a signal transition. Addressing this issue, Sugawara et al. proposed to use a mirror circuit that has the same number of transistors on its possible current paths. We show that this countermeasure is insufficient by showing a new transistor-level leakage, caused by RECs, not covered in the previous work. RECs can carry the history of the gate's state over multiple clock cycles and changes the gate's electrical behavior. We experimentally verify that RECs cause exploitable side-channel leakage. We also propose a countermeasure against REC leaks and designed advanced encryption standard-128 (AES-128) circuits using IO-masked dual-rail read-only memory with a 180-nm complementary metal-oxide-semiconductor (CMOS) process. We compared the resilience of our AES-128 circuits against EMA attacks with and without our countermeasure and investigated an RECs' effect on physically unclonable functions (PUFs). We further extend RECs to physically unclonable function. We demonstrate that RECs affect the performance of arbiter and ring-oscillator PUFs through experiments using our custom chips fabricated with 180- and 40-nm CMOS processes*.

Shrink Generator-based Strong PUF Architecture with Improved Uniqueness and Reliability on an FPGA

Silicon-based Physically Unclonable Functions (PUFs) are a source of physical security primitive that is either implemented on ASICs or FPGAs. A class of these security primitives that provide an exponentially large set of Challenge- Response Pairs (CRPs) is termed Strong PUF. That notwithstanding, the Arbiter and Feedforward Arbiter PUFs which are traditionally Strong PUFs, are not suitable for FPGA implementation. In this paper, a newly proposed PUF architecture that improves on the existing Configurable Ring Oscillator (CRO) PUF by increasing its dynamic configurability and its level of entropy is presented. To maintain the exponentially large set of CRPs, the Shrink Generator is applied to the traditionally Weak CRO-PUF. The proposed design is implemented and tested on a spartan-6 FPGA board using the Xilinx ISE tool. The proposed architecture demonstrates a uniqueness of 50.01% and is 96.43% reliable.

MCRO-PUF: A Novel Modified Crossover RO-PUF with an Ultra-Expanded CRP Space

With the expanding use of the Internet of Things (IoT) devices and the connection of humans and devices to the Internet, the need to provide security in this field is constantly growing. The conventional cryptographic solutions need the IoT device to store secret keys in its non-volatile memory (NVM) leading the system to be vulnerable to physical attacks. In addition, they are not appropriate for IoT applications due to their complex calculations. Thus, physically unclonable functions (PUFs) have been introduced to simultaneously address these issues. PUFs are lightweight and easy-to-access hardware security primitives which employ the unique characteristics of integrated circuits (ICs) to generate secret keys. Among all proposed PUFs, ring oscillator PUF (RO-PUF) has had a more suitable structure for hardware implementation because of its high reliability and easier providing of circuital symmetry. However, RO-PUF has not been so attractive for authentication purposes due to its limited supported challenge-response pairs (CRPs). A few efforts have been made in recent years that could successfully improve the RO-PUF CRP space, such as configurable RO-PUF (CRO-PUF). In this paper, by considerably improving the CRO-PUF structure and adding spare paths, we propose a novel strong RO-PUF structure that exponentially grows the CRP space and dramatically reduces the hardware cost. We implement our design on a simple and low-cost FPGA chip named XC6SLX9-2tqg144, stating that the proposed design can be used in IoT applications. In addition, to improve the CRP space, our design creates a suitable improvement in different security/performance terms of the generated responses, and dramatically outperforms the state-of-the-art. The average reliability, uniqueness, and uniformity of the responses generated are 99.55%, 48.49%, and 50.99%, respectively.

Suitability of Generalized GAROs on FPGAs as PUFs or TRNGs Considering Spatial Correlations

In the last years, guaranteeing the security in IoT communications has become an essential task. In this paper, the bias of a wide set of oscillators has been studied to determine their suitability as both True Random Number Generators (TRNGs) and Physically Unclonable Functions (PUFs). For this purpose, a generic configurable structure has been proposed and implemented in an FPGA. With this implementation, by introducing some external signals it is possible to configure the system in different oscillator topologies. This way, we have managed to analyze 2730 oscillators composed by 7 Lookup Tables (LUTs) without having to resynthesize the code each time. The performed analysis has included conventional ring oscillators, Galois ring oscillators and newly proposed oscillator topologies. From this analysis we have concluded that none of these oscillators behave as an ideal TRNG but ring oscillators present the closest to an ideal behavior. Regarding their suitability as PUFs, some of the newly proposed oscillators in this paper present a high reproducibility, higher than that of conventional ring oscillator PUF (RO-PUF) and a high uniqueness. Furthermore, we have noticed that both their reproducibility and their uniqueness tend to improve when increasing the length of the oscillators, which opens the possibility of finding new oscillators with even better properties by studying oscillators of bigger lengths. Finally, by studying the spatial correlation of the bias of these oscillators, we have observed that they present a much lower spatial correlation compared to the ring oscillators, which opens the possibility of using these oscillators in PUF architectures that use more comparisons than typical RO-PUFs.

True Random Number Generation Capability of a Ring Oscillator PUF for Reconfigurable Devices

This paper presents the validation of a novel approach for a true-random number generator (TRNG) based on a ring oscillator–physical unclonable function (RO-PUF) for FPGA devices. The proposal takes advantage of the different noise sources that affect the electronic implementation of the RO-PUF to extract the entropy required to guarantee its function as a TRNG, without anything more than minimal changes to the original design. The new RO-PUF/TRNG architecture has been incorporated within a hybrid HW/SW embedded system designed for devices from the Xilinx Zynq-7000 family. The degree of randomness of the generated bit streams was assessed using the NIST 800-22 statistical test suite, while the validation of the RO-PUF proposal as an entropy source was carried out by fulfilling the NIST 800-90b recommendation. The features of the hybrid system were exploited to carry out the evaluation and validation processes proposed by the NIST publications, online and on the same platform. To establish the optimal configuration to generate bit streams with the appropriate entropy level, a statistical study of the degree of randomness was performed for multiple TRNG approaches derived from the different implementation modes and configuration options available on the original RO-PUF design. The results show that the RO-PUF/TRNG design is suitable for secure cryptographic applications, doubling its functionality without compromising the resource–efficiency trade-off already achieved in the design.

Design and analysis of DDoS mitigating network architecture.

Distributed Denial of Service (DDoS) attacks have emerged as the top security threat with the rise of e-commerce in recent years. Volumetric attacks are the most common DDoS attacks that aim to overwhelm the victim's bandwidth. The current mitigation methods use reactive filtering techniques that are not magical and straightforward solutions. In this paper, we propose a network architecture based on the capability to address the threat of DDoS attacks. Physically Unclonable Functions (PUFs) have emerged as a promising solution in security. Motivated by the capability approach, we put forward a network architecture where the routers use Transient Effect Ring Oscillator PUF to generate and verify capabilities. This novel hardware-based solution, to address the problem, has reduced the computational overhead of capability generation. Additionally, the destination has complete control over the incoming traffic in the proposed architecture, resulting in uninterrupted communication with the legitimate clients regardless of the attacker traffic. The large-scale simulation on an open-source Network Simulator (NS-3) has shown that the proposed architecture efficiently mitigates DDoS attacks to a large extend. With our proposed architecture, the throughput was hardly affected when attacker traffic was varied from 10 to 80%.

Redshift: Manipulating Signal Propagation Delay via Continuous-Wave Lasers

We propose a new laser injection attack Redshift that manipulates signal propagation delay, allowing for precise control of oscillator frequencies and other behaviors in delay-sensitive circuits. The target circuits have a significant sensitivity to light, and a low-power continuous-wave laser, similar to a laser pointer, is sufficient for the attack. This is in contrast to previous fault injection attacks that use highpowered laser pulses to flip digital bits. This significantly reduces the cost of the attack and extends the range of possible attackers. Moreover, the attack potentially evades sensor-based countermeasures configured for conventional pulse lasers. To demonstrate Redshift, we target ring-oscillator and arbiter PUFs that are used in cryptographic applications. By precisely controlling signal propagation delays within these circuits, an attacker can control the output of a PUF to perform a state-recovery attack and reveal a secret key. We finally discuss the physical causality of the attack and potential countermeasures.

CT PUF: Configurable Tristate PUF Against Machine Learning Attacks for IoT Security

Physical unclonable function (PUF) is a promising lightweight hardware security primitive for resource-limited Internet-of-Things (IoT) devices. Strong PUFs are suitable for lightweight device authentication because it can generate quantities of challenge-response pairs. Unfortunately, while the machine learning (ML) techniques have benefited various areas, such as Internet, industrial automation, robotics and gaming, they pose a severe threat to PUFs by easily modelling their behavior. This article first shows that even a recently reported dual-mode PUF can be cloned by ML (prediction accuracy of up to 95%). To solve this issue, we propose a configurable tristate (CT) PUF which can flexibly perform as an arbiter PUF, a ring oscillator (RO) PUF, or a bistable ring (BR) PUF with a bitwise XOR-based mechanism to obfuscate the relationship between the challenge and the response, hence resisting the ML attacks. An authentication protocol for the use in IoT security is presented. The CT PUF is implemented on Xilinx ZedBoard FPGAs with placement and routing details described. The experimental results show that the modelling accuracy of logistic regression (LR), support vector machine (SVM), covariance matrix adaptation evolutionary strategies (CMA-ES), and artificial neural network (ANN) is close to 60% (50% as the ideal number in theory) while meeting the PUF requirements for uniformity, reliability, and uniqueness. The hardware overhead and power consumption are slight. The entire project has been open sourced.

Concealable Oscillation-Based Physical Unclonable Function With a Single-Transistor Latch

A concealable oscillation-based physical unclonable function (CO-PUF) with a FinFET is demons- trated for high-level security. The CO-PUF FinFET can significantly reduce both the footprint and the hardware cost of the components that generate the oscillating signal compared to a ring-oscillator PUF (RO-PUF) circuitry. The CO-PUF is based on random oscillation, which is attributed to a single-transistor latch (STL). Random bits are encoded as binary states of “1” and “0” depending on whether a CO-PUF FinFET shows oscillation or not. It satisfies the demand of randomness, uniqueness and stability. Additionally, the encryption key is untraceable with a key cloaking function when hacking is attempted.

Jorge Fernández - Ring Oscillator PUF on FPGA: Design and Characterisation by Using Second-Order Compensated Measurement

Ring Oscillator PUF on FPGA: Design and Characterisation by Using Second-Order Compensated Measurement