RF CMOS Technology Research Articles

LINEARITY IMPROVEMENT OF CASCODE CMOS LNA USING A DIODE CONNECTED NMOS TRANSISTOR WITH A PARALLEL RC CIRCUIT

A fully integrated 5.5GHz high-linearity low noise amplifler (LNA) using post-linearization technique, implemented in a 0.18m RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise flgure (NF) and power consumption. The LNA achieves an input third-order intercept point (IIP3) of +8:33dBm, a power gain of 10.02dB, and a NF of 3.05dB at 5.5GHz biased at 6mA from a 1.8V power supply.

A Low Power V-Band Injection-Locked Frequency Divider in 0.13-.MU.m Si RFCMOS Technology

In this work, a divide-by-2 injection locked frequency divider (ILFD) operating in the V-band with a low DC power consumption has been developed in a commercial 0.13-µm Si RFCMOS technology. The bias current path was separated from the injection signal path, which enabled a small supply voltage of 0.5V, leading to a DC power consumption of only 0.31mW. To the authors' best knowledge, this is the lowest power consumption reported for mm-wave ILFDs at the point of writing. All inductors and interconnection lines were designed based on EM (electromagnetic) simulator for precise prediction of circuit performance. With varactor tuning voltage ranged for 0-1.2V, the free-running oscillation frequency varied from 27.43 to 28.06GHz. At 0dBm input power, the frequency divider exhibited a locking range of 5.8GHz from 53 to 58.8GHz without external tuning mechanism. The fabricated circuit size is 0.72mm × 0.62mm including the RF and DC supply pads.

The Enhanced Role of Shallow-Trench Isolation in Ionizing Radiation Damage of 65 nm RF-CMOS on SOI

The mechanism for ionizing radiation damage in multi-finger SOI CMOS devices is presented for the first time. We analyzed the effects of shallow-trench isolation on ionizing radiation response of 65 nm Silicon-On-Insulator (SOI) CMOS technology. The radiation response of the CMOS devices was investigated using 63 MeV protons and 10 keV X-rays. The implications of proton irradiation and X-ray irradiation on the dc and RF performance of these devices are presented. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. Even though there is charge-accumulation in the buried-oxide, there is minimal impact on the front-gate characteristics of the partially-depleted SOI devices in this 65 nm CMOS technology. The implications of parasitic conduction along the STI on device design constraints, particularly for varying device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that body-contacting schemes which eliminate sidewalls (e.g., H-body, T-body) will provide the necessary total-dose radiation tolerance for multi-finger analog and RF devices, without additional hardening techniques.

A multiple-pass ring oscillator based dual-loop phase-locked loop

A dual-loop phase-locked loop (PLL) for wideband operation is proposed. The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one, enabling a wide tuning range and low voltage-controlled oscillator (VCO) gain without poisoning phase noise and reference spur suppression performance. An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized. A novel multiple-pass ring VCO is designed for the dual-loop application. It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology. The measured tuning range is from 4.2 to 5.9 GHz. It achieves a low phase noise of –99 dBc/Hz @ 1 MHz offset from a 5.5 GHz carrier.

A 60-GHz Phased Array Receiver Front-End in 0.13-$\mu {\hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS technology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capacitance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resistance is 50 Ω, and the average input noise current spectral density is 9.7 pA/√Hz. Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

An area-saving dual-path loop filter for low-voltage integrated phase-locked loops

This paper proposes an area-saving dual-path loop filter (LPF) for low-voltage integrated phase-locked loops (PLLs). With this LPF, output current of the lowpass-path charge-pump (CP) is B times (B > 1) as great as that of the integration-path CP. By adding voltages across these two paths, the zero-capacitance is magnified B times equivalently. As a result, the chip size is greatly reduced. Based on this LPF, a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18 μm RFCMOS technology. Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that, at a frequency of 3.20 GHz, phase noise is –120.2 dBc/Hz at 1 MHz offset, reference spur is –72 dBc, and power is 24 mW.

High-performance current bleeding CMOS mixer

A high-performance mixer, known as the amplifier-driven double-balanced Gilbert-cell mixer, is proposed and implemented in 0.18 µm RFCMOS technology. A class-A amplifier-based current bleeding source is used to amplify the local oscillator signal and improve transconductance of the transconductor stage. The conversion gain is measured to be 17.5 dB when the LO power is −14 dBm only. The measured noise figure is better than 12.5 dB. The chip area is 1.2×1.3 mm and the power consumption is 12 mA at 1.5 V supply voltage.

Radio transceivers for wireless personal area networks using IEEE802.15.4

This article describes the design considerations for low-power short-range radio transceivers with a focus on the 2.4 GHz PHY layer defined as part of the IEEE 802.15.4 standard. The specification requirements for IEEE 802.15.4-compliant transceivers, and the design challenges and practical implementation of a highly-integrated low-power 2.4 GHz transceiver are subsequently discussed. The transceiver uses a direct-conversion receiver with switched antenna diversity and a transmitter using direct closedloop VCO modulation. It integrates a mask-programmable radio controller capable of autonomously performing timing-critical MAC functions, and a sleep timer. Implemented in 0.18 mum RFCMOS technology with a chip area of less than 6 mm2, the transceiver achieves a link margin of 99 dB while drawing 16.8 mA and 18 mA from a 1.8 V supply in receive and transmit mode, respectively.

Impact of Proton Irradiation on the RF Performance of 65 nm SOI CMOS Technology

The effects of 63 MeV proton irradiation on 65 nm Silicon-On-Insulator (SOI) CMOS technology are presented for the first time. The radiation response of the CMOS devices was investigated up to an equivalent total gamma dose of 4.1 Mrad (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). We analyze the implications of proton irradiation on RF performance of these devices. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. High-frequency measurements show that the input and output matching conditions are not affected, up to a cumulative dose of 4.1 Mrad. The implications of proton irradiation on device design constraints, particularly device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that multi-finger CMOS devices with higher finger width are better-suited for the development of total-dose radiation tolerant analog and RF circuits without additional radiation hardening.

A 4.39–5.26 GHz LC-Tank CMOS Voltage-Controlled Oscillator With Small VCO-Gain Variation

A wide band CMOS LC-tank voltage controlled oscillator (VCO) with small VCO gain ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">KVCO</i> ) variation was developed. For small <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">KVCO</i> variation, serial capacitor bank was added to the LC-tank with parallel capacitor array. Implemented in a 0.18 mum CMOS RF technology, the proposed VCO can be tuned from 4.39 GHz to 5.26 GHz with the VCO gain variation less than 9.56%. While consuming 3.5 mA from a 1.8 V supply, the VCO has -113.65 dBc/Hz phase noise at 1 MHz offset from the carrier.

Low voltage low noise open loop automatic amplitude control for voltage-controlled oscillators

This paper presents a low voltage low noise open loop automatic amplitude control method for voltage-controlled oscillators (VCO's). In this method a feedback mechanism keeps the VCO at its optimum amplitude over temperature and process variations and then the loop is broken to avoid noise injection form the control circuitry to the VCO. The loop does not add extra noise to the VCO. Based on the proposed method, a low voltage low noise LC-VCO was designed for a low phase noise application in TSMC 0.18 micron RFCMOS technology. Simulations show considerable improvement in the phase noise with the application of the proposed method.

A fractional-N frequency synthesizer for WCDMA/Bluetooth/ZigBee applications

A triple-mode fractional-N frequency synthesizer with a noise-filter voltage controlled oscillator (VCO) for WCDMA/Bluetooth/ZigBee applications has been implemented in 0.18-μm RF-CMOS technology. The proposed synthesizer achieves a good phase noise lower than −80 dBc/Hz in band and −115 dBc/Hz@1 MHz for the three modes, and only draws 21 mA from a 1.8 V supply. It has a high hardware sharing and a small size, only 1.5 × 1.4 mm2. The system architecture, circuit design, and measured results are also presented.

RF-CMOS技術のセンサへの展開 : 測定システムの集積化(インタラクティブシステム・画像入力デバイス・方式,及び一般)

RF-CMOS技術のセンサへの展開 : 測定システムの集積化(インタラクティブシステム・画像入力デバイス・方式,及び一般)

A single-poly EEPROM cell for embedded memory applications

We present a novel single-poly-silicon EEPROM cell for embedded memory. The cell is integrated in a 0.13μm RF-CMOS technology without process modifications and is composed of an NMOS transistor and a MOS capacitor on two isolated P-wells sharing a floating poly-silicon layer. A two-polarity voltage of ±6V is applied for writing and erasing using uniform-channel Fowler–Nordheim tunnelling. Operations faster than 1ms, endurance over 10+3 cycles and data retention longer than 10 years are demonstrated.

RF Model of BEOL Vertical Natural Capacitor (VNCAP) Fabricated by 45-nm RF CMOS Technology and Its Verification

A radio-frequency equivalent circuit model for the symmetric vertical natural capacitor (VNCAP) in a 45 nm low-standby-power CMOS process is presented. The average effective capacitance density of 2.24 fF/ mum2 is obtained from VNCAPs of 1 times (M1 - M5) + 2 times (M6 - M7) metal-layer configuration after the open-short de-embedding procedure. The proposed model consists of main series capacitance network and lossy substrate network. The accuracy of the VNCAP model is verified S-parameters, effective capacitance Ceff, and quality factor (Q) up to 15 GHz. The proposed model can accurately describe the frequency characteristics of S-parameters, Ceff, and Q-factor up to 15 GHz for VNCAPs with different widths and lengths.

A CMOS 4.1 GHz two-stage cascode LNA with ESD protection

A 4.1 GHz two-stage cascode Low-Noise Amplifier (LNA) with Electro-Static Discharge (ESD) protection is presented in this paper. The LNA has been optimized using ESD and LNA co-design methodology to achieve a good performance. Post-layout simulation results exhibit a forward gain (S21) of about 21 dB, a reverse isolation (S12) of less than −18 dB, an input return loss (S11) of less than −16 dB, and an output return loss (S22) of less than −17 dB. Moreover, the Noise Figure (NF) is 2.6 dB. This design is implemented in TSMC0.18μm RF CMOS technology and the die area is 0.9 mm × 0.9 mm.

A Physics-Based Equivalent-Circuit Model for On-Chip Symmetric Transformers With Accurate Substrate Modeling

A physics-based equivalent-circuit model for on-chip symmetric transformers is presented with all the model elements driven from fabrication specifications. Two extra coupled transformer loops are used for each coil to model the parameters of skin effect, proximity effect, and reflective effect of the substrate eddy current, respectively. Model accuracy under free space is first demonstrated using an electromagnetic field solver without considering substrate loss. Several sets of transformers were fabricated on a standard 0.18- mum 1P8M RF CMOS technology to further verify the accuracy and scalability of the proposed model. By careful comparison of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameters, coil inductance, quality factor,coupling coefficient, and maximum available gain between measured data and simulated data, model accuracy, and scalability are verified over a wide range of geometry configurations.

Modeling and Characterization of Intermodulation Linearity on a 90-nm RF CMOS Technology

This paper presents measured, simulated and calculated third-order intercept point (IP3) on a 90-nm RF CMOS technology. The IP3 sweet spot is actually at a <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> lower than zero <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</i> 3 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</i> point. This <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> difference is attributed to the nonlinear output conductance and the cross terms using a Volterra-series-based IP3 expression. The impact of these nonlinearities is quantified using simulated <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I-V</i> and device small-signal parameters extracted from <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameter simulation. The scaling factors of the nonlinearities causes a decrease of IP3 sweet spot <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> as device size increases. The IP3 expression can accurately predicts the device size dependence of IP3 sweet spot. The frequency dependence of IP3 is determined by the small signal capacitance. Thus, the frequency dependence is very weak and negligible for a small device. For a large device, not only gate-source capacitance and drain-bulk capacitance, but also gate-drain capacitance are important. To determine the value of IP3 accurately, a more complete equivalent circuit of the MOS transistor must be used in Volterra-series analysis. The <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> dependence of the IP3 sweet spot <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> is primarily due to drain induced barrier lowering.

Design of an adaptive LNA for hand‐held devices in a 1‐V 90‐nm standard RF CMOS technology: From circuit analysis to layout

This paper deals the design of a reconfigurable Low‐Noise Amplifier (LNA) for the next generation of wireless hand‐held devices by using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing the fulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such that the mathematical design flow is simple as well as suitable for hand‐work in both laboratory and classroom. The circuit under analysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two‐stage topology including inductive‐source degeneration, MOS-varactor based tuning networks, and programmable bias currents. This proposal, with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications; the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b‐g). In order to evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA features NF&lt;1.77dB, S21&gt;16dB, S11&lt;-5.5dB, S22&lt;-5.5 dB and IIP3&gt;-3.3 dBm over the 1.85-2.48 GHz band. For all the standards under study the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1‐V. The layout of the reconfigurable LNA occupies an area of 1.8mm2.