RF CMOS Technology Research Articles

Highly Linear RMS Microwave Power Sensor Joule-Heating-Based Using CMOS Technology

This article presents the design and implementation of a high-power handing capacity, wideband, and excellent microwave-dc linearity root-mean-square (rms) microwave power sensor (PS) in 180-nm standard RF CMOS technology. The detection technique utilizes two well-matched microwave power absorbers and a balanced Wheatstone full bridge (WFB) with thermistors to produce a dc output proportional to incident microwave power. The lateral spacing between the hot and cold zones of WFB with 80, 100, 120, 140,and 160 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu}$</tex-math> </inline-formula> m has been investigated experimentally, which provides insight into the proper adjustment of the layout parameters. The experimental result of the vector network analyzer (VNA) shows that the input reflection loss is less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 22.3 dB in the frequency range of 0–20 GHz. This indicates that the designed microwave PSs have good impedance matching characteristics. Moreover, it is demonstrated that the inherent linear relationship between the output dc voltage and the incident microwave power is less than 1.6% over a dynamic range of 1–500 mW. The proposed microwave PS can be further integrated in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{X}$</tex-math> </inline-formula> -band RF transceivers, offering high microwave-dc linearity, acceptable sensitivity, small size, and low cost for improving power transfer efficiency and optimizing the performance of the transmitting and receiving chain.

Ultra Low Power Temperature Compensated Complementary Metal Oxide Semiconductor Ring Oscillator in Subthreshold

Low power consumption, low chip area and fabrication in the standard complementary metal oxide semiconductor (CMOS) process are vital requirements for oscillators used in low-cost bio-implantable and wearable devices. Conventional ring oscillators (ROs) are good candidates for using in biomedical applications. However, their oscillation frequency strongly depends on the temperature. In this study, a temperature compensated ring oscillator with low power consumption is proposed. The transistors of the proposed ring oscillator operate in the subthreshold region to achieve a low power and low voltage performance. Since, in the subthreshold region, the oscillation frequency of a conventional ring oscillator increases with increase in the temperature, two current sources are used to power the proposed subthreshold ring oscillator: a temperature independent current source and a complementary to absolute temperature (CTAT) current source. In the proposed circuit, the CTAT current forms a small part of the total supplied current and its duty is to compensate for the oscillation frequency deviation. Two prototypes of the subthreshold ring oscillator were designed and simulated for a target frequency of 1MHz using commercially available 0.18µm RF-CMOS technology. The thermal coefficient (TC) of the uncompensated ring oscillator was 2400 ppm/ºC from -40ºC to 85ºC, though applying the proposed technique reduces the TC of the ring oscillator to 80.4 ppm/ºC with total power consumption as low as 14.5µW.

고선형성 저전력 24-GHz 저잡음 증폭기 개발

This paper presents a high-linearity low-power 24-GHz CMOS low noise amplifier (LNA). The LNA was designed and implemented using 65 nm RF CMOS technology. The circuit was powered by a 1.2 V supply and operated at a frequency of the 24 GHz. To reduce noise and nonlinearity, an inductor was connected to the gate of the cascode transistor and combined with capacitive cross-coupling. The proposed LNA was fabricated with a maximum OIP3 of 21.8 dBm, lowest power consumption of 6 mW, lowest noise figure of 2.9 dB, and smallest die size of 0.31×0.34 mm².

An Inductorless Gain-Controllable Wideband LNA Based on CCCIIs.

In this paper, an inductorless and gain-controllable 0.5~2.5 GHz wideband low noise amplifier (LNA) based on second generation current controlled current conveyors (CCCIIs) is presented. The proposed wideband LNA utilizes CCCIIs as building blocks to implement the amplifier stage and impedance matching stage. By varying the DC biasing current of the CCCII, the voltage gain of the proposed LNA is controllable in the range of 1~18 dB. In the frequency range of 0.5~2.5 GHz, the post-layout simulation results show that the proposed LNA has a typical voltage gain S21 of 12.6 dB with a gain ripple of ±1.5 dB, an input and output return loss (S11 and S22) of, respectively, -21.4 dB to -16.6 dB and -18.6 dB to -10.6 dB, and a high reverse isolation S12 of -65.2 dB to -39.5 dB. A noise figure of 4.05~4.35 dB is obtained across the whole band, and the input third-order intercept point (IIP3) is -2.5 dBm at 1.5 GHz. Using a 0.18 μm RF CMOS technology, the LNA occupies an active chip area of only 0.096 mm2 with a power consumption of 12.0 mW.

Design of Common Gate Current-Reuse Noise Cancellation UWB Low Noise Amplifier in 90nm CMOS

In this paper, an ultra-wide band (UWB) low noise amplifier (LNA) is implemented by using 90nm RF CMOS technology. The designed LNA achieves high flat band gain (S21) and low noise figure (NF) in the frequency of interest. The proposed LNA operates in the frequency range of 3GHz to 8GHz. In this work, wide band matching is achieved by designing common gate configuration at the input stage. The current reuse and noise cancellation techniques are introduced to improve flat band gain and minimize both noise figure and power consumption. The noise figure is improved by cancelling dominant noise sources with additional hardware. The proposed LNA attains flat band gain of 26.5dB and input matching less than -12dB for entire UWB band. This work achieves noise figure of 2.1dB to 2.59dB in frequency band of interest. Additionally, power consumption of the circuit is 20mW at 1.8V supply voltage.

A Compact 6-bit Phase Shifter in 65 nm RF CMOS Technology for ISM Band

We presented a 6-bit switched-network type phase shifter, which was implemented in Samsung 65nm RF CMOS technology. The phase shifter was designed with lumped-element filter topologies using inductors and capacitors for compact size. For 64 states, in the frequency of 2.12 GHz - 2.51 GHz, measured insertion loss was -9.7±1.5 dB. The input and output return loss were above 8.2 dB and 10 dB, respectively. The rms phase error and rms amplitude error were less than 3° and 0.87 dB, respectively. The chip size with including pads was 1.4 × 0.81 mm².

Current-Reuse Active Inductor-Based VCO for Reconfigurable RF Front-End

This paper deals with the design of a current-reuse active inductor. Current-reuse active inductor-based voltage-controlled oscillator (CRAI-VCO) with a wide tuning range is designed based on the proposed active inductor. The tuning range of VCO is from 1.25 to 2.5 GHz giving a tuning percentage of 68% at a power consumption of 5 mW. The phase noise obtained is −100 dBc/Hz. The post-layout simulations are carried out in Cadence Virtuoso using UMC 180 nm RFCMOS technology. The circuit occupies an active area of 143 µm × 148 µm. The figure of merit of VCO considering the frequency tuning range is −177.3 dBc/Hz comparable to other state-of-the-art VCO designs.

A low‐noise current‐reused CMOS active inductor by exploiting G m ‐boosting technique

This work introduces a new low-noise current-reused CMOS active inductor (AI) based on Gyrator-C configuration. In the proposed AI, a simple common-source amplifier is utilised for boosting effective Gm and improving noise performance of the AI. While the Gm-boosting technique improves the noise performance as well as the quality factor of the inductor, a resistor is also added to the feedback path for more quality factor improvement. Rigorous analysis of the proposed circuit shows a significant noise performance and quality factor enhancement. In order to verify the concept and confirm the mathematical analysis, the AI is designed and simulated in a commercial 0.18 μm RF-CMOS technology. The simulation results show that the proposed inductor operates in 1 to 7.2 GHz frequency range, has a 9 nH inductance at 2.864 GHz frequency and 650 μW total power dissipation at 1.8-V supply voltage. Maximum quality factor of 90 is achieved at 2.864 GHz frequency and a quality factor greater than 40 is obtained from 2.4 to 3.3 GHz. The input-referred current noise of the proposed inductor is as low as 22 pA / √ Hz showing 30.5% improvement compared to the conventional AI. The proposed AI is also tunable and sweeping the tuning voltage results in changing extracted inductance from 4.35 to 15.2 nH with only a chip area of 0.003 mm2. Post-layout and different Monte Carlo simulation results also confirm the robust operation of the proposed AI against different process non-idealities.

Design and application of CMOS active inductor in bandpass filter and VCO for reconfigurable RF front-end

This paper presents the design of gyrator-C active inductor. Current reuse technique reduces the noise of transconductor in gyrator. Bandpass filter and voltage-controlled oscillator (VCO) are designed based on the proposed active inductor. Post-layout simulations and PVT analysis are carried out using 180 nm RFCMOS technology at 1.8 V supply voltage. Bandpass filter with center frequency 2.45 GHz attains a noise figure of 6 dB. VCO with a tuning range of 1.5 GHz–2.8 GHz attains a phase noise of −99.86 dBc/Hz. The active area occupied by bandpass filter and VCO are 150 μm × 150 μm and 145 μm × 145 μm respectively.

Analysis and design of ultra‐wideband low noise amplifier using complementary structure with series inductive peaking technique and shunt feedback

SummaryIn this paper, an ultra‐wideband low noise amplifier (LNA) is presented using 0.18‐μm RF CMOS technology. A complementary structure with series inductive peaking technique is introduced by using two inductor‐loops to achieve flat gain. In the first and third stages, two complementary structures are utilized to achieve a high and flat gain, a wideband input impedance matching and a low noise figure. In addition, a shunt feedback is utilized to increase input impedance matching and stability. In the second stage, a common source structure is used as interstage, which increases the −3 dB bandwidth. The designed LNA presents a high and flat gain of 15.6–16.5 dB, an excellent input return loss better than −11 dB and a good NF of 2.2–3 dB in the frequency range of 3.1–10.6 GHz. Also, the proposed structure consumes 6.8 mW from a 0.8‐V supply voltage and has an IIP3 of −4 dBm at 6.5 GHz. The proposed structure only occupies 0.59 mm2.

A C-band low-power sub-1volt current-reused multiphase oscillator

A new sub-1V and low power multiphase voltage-controlled oscillator (QVCO) with current-reused structure is proposed. The proposed core oscillator consists of two N-metal oxide semiconductor (NMOS) and P-metal oxide semiconductor (PMOS) transistors and an additional NMOS-only cross-coupled pair that enhances the effective negative transconductance and facilities the start-up condition at sub-1V supply voltages in modern nm CMOS technologies. In the proposed coupling scheme, the gate of cross-coupled transistors is used for coupling in an ‘in-phase−anti-phase’ manner. Parallel capacitors to the drain-source of transistors have been used for further enhancement of effective transconductance and thus lower power consumption; though the increase of parallel capacitors reduces the tuning range, indicating a trade-off in the proposed QVCO. The proposed quadrature oscillator is designed and simulated in a standard 0.18 μm RF-CMOS technology. The results of the simulation show that the QVCO has a 9% tuning range from 5.35 GHz to 5.88 GHz, and the phase noise is −119.6 dBc/Hz at 1-MHz offset from the 5.7 GHz carrier while consumes only 1.4 mW from a 0.85-V supply voltage; yielding an excellent figure-of-merit (FOM) of −193.3 dBc that is amongst the best FOMs. Several Monte Carlo and PVT analyses verify the robust performance of the QVCO.

High-Resolution and Large-Detection-Range Virtual Antenna Array for Automotive Radar Applications.

Collision avoidance and autonomous control of vehicles have become essential needs for providing a high-quality and safe life. This paper introduces a new generic scheme for a virtual antenna array (VAA) and its application in a train collision-avoidance system (TCAS). The proposed TCAS shall have the capability of identifying the range and angle of an object in front of a moving train and provide the required alerts. Thereby, a new virtual array distribution for both the transmitting and the receiving antenna arrays is introduced to get a long-range object detection and high-resolution multi-input multi-output (MIMO) system. This can be accomplished because the VAA radiation pattern is the multiplication of the radiation patterns for both the transmitting and receiving antenna arrays, which is different than each one of them alone. In this work, the VAA is utilized in radar systems in which the radar range depends on the multiplication of the gain of the transmitting and receiving antennas. So, we introduce a new scheme for the general design of VAA-based radars. A prototype for the antenna system was fixed on a of Texas Instruments platform for the cascading radar. One of the main problems of the VAA is the loss of radiated power in undesired directions, which affects the maximum detection range in beamforming systems and degrades the diversity gain in MIMO applications. These issues have been solved by the introduction of the practical implementation of a proposed high-gain, low side lobe level VAA system for automotive radar that is based on the integration of four AWR1243 RF chips operating in a frequency range of 76 GHz to 81 GHz. It was implemented using low-power 45 nm (TI) RFCMOS technology. The measured gain of the realized VAA was 47.2 dBi, which was 1.815 times higher than that of the Texas instrumentation linear frequency modulated continuous wave (TI’ LFMCW) radar, which was 26 dBi. The proposed VAA saved 45% of the required implementation area compared to the TI’ LFMCW antenna array. The VAA system was fabricated and tested in an anechoic chamber, and it was found that the simulated and measured patterns of the proposed VAA were highly matched in terms of half-power beamwidth and side lobe level.

BISH–QVCO: A Low–Power, Low–Phase noise Bulk–Injected Super–Harmonic coupling QVCO

In this paper, a novel method of Super–Harmonic coupling is proposed to generate quadrature outputs. In this method, by direct connection of all switching transistors bulk terminals, a second harmonic current is injected from each one of the I/Q oscillators to the other. Therefore, the proposed circuit is called Body–Injected Super–Harmonic coupling (BISH–) QVCO. The quadrature operation of the proposed circuit is mathematically proven and certified by simulations. In addition, through a detailed analysis, closed–form expressions are derived for the output phase noise and phase error. To have a fair performance evaluation of the proposed topology, the proposed BISH-QVCO, and the conventional P–QVCO are designed and simulated in 0.18 ​μm RF-CMOS technology with 3.22–3.64 ​GHz oscillation frequency (12.25% tuning range), a power supply of 1.8V, and the same power consumption of 3.85 ​mW. The quality factor of the tank circuits is calculated as 9.2. Post layout simulation results predict phase noise of −122.3dBc/Hz at 1 ​MHz offset from 3.64 ​GHz oscillation frequency that presents 4.1 ​dB and 2.7 ​dB phase noise improvements compared to the conventional P–QVCO and simple LC VCO, respectively. The maximum I and Q outputs phase error due to a 2% tank capacitor mismatch is 7°. A FOMT of 189.4 ​dB is achieved for the proposed QVCO. Also, the proposed method is capable of generating multi–phase outputs, which can be ranked among the well-performing ones.

A 36.7 mW, 28 GHz receiver frontend using 40 nm RFCMOS technology with improved Figure of Merit

High carrier frequency requirement (Sub 6, 28 GHz) to accomplish the high bandwidth specification for millimeter wave band wireless communication, has reduced the ratio of operating carrier frequency (fc) and unity current gain frequency (ft) of MOSFETs in state of the art RFCMOS technology. This poses a challenge for designing a high gain and low noise receiver with better linearity. In an attempt to realize such receiver, this paper presents a 28 GHz receiver front-end in 40 nm RFCMOS technology. It includes 3-stage low noise amplifier incorporating push pull topology, current bleeding down converting gilbert cell based mixer with common gate transconductance stage followed by a standard Gm-C filter. By incorporating these techniques, the performance of the proposed receiver improved in terms of linearity as compared to the state of the art designs. For a comprehensive analysis, the combined effect of performance parameters has been compiled into a single metric i.e. Figure of Merit (FOM). The proposed receiver exhibits conversion gain of 30.5 dB and 2.15 dB noise figure with linearity parameter IIP3 being −21.7 dBm while consuming 36.7mW power resulting in FOM value of 0.27.

Comparison of parameters of ring and LC-tank digitally controlled oscillators in 0.13 µm CMOS

Abstract Integrated circuits (IC) of two digitally controlled oscillators (DCO) are presented in this article – ring and LC-tank oscillator. Main parameters of these DCOs are measured and compared, applications of such DCOs are discussed. Ring DCO is made of 48 sections of 3-stage ring oscillators. Base component of ring oscillator is tristate inverter, which is accessible in modern CMOS technologies, therefore, such oscillator can be implemented using digital IC design tools. Main components of LC-tank DCO are inductor, switched-capacitor bank, and a pair of cross-coupled NMOS transistors. Frequency of ring DCO is controlled by enabling or disabling its separate sections, while frequency of LC DCO is controlled by switching capacitors of LC tank. Although LC DCO is controlled digitally, its core is analog and it can be implemented only using custom design tools. Both DCOs are designed and their prototypes are manufactured in mature and low-cost 0.13 μm RF CMOS technology. Ring DCO’s frequency tuning range is 370–873 MHz; phase noise at maximum operating frequency at 1 MHz offset from carrier is – 109.19 dBc/Hz; power consumption is 3.6 mW; used area of silicon is 0.0065 mm2. LC-tank DCO’s frequency tuning range is 9.26–10.58 GHz; phase noise at maximum operating frequency at 1 MHz offset from carrier is –106.46 dBc/Hz; power consumption is 18 mW; used area of silicon is 0.06 mm2. Operating frequency of LC-tank DCO is much higher, however Figures of Merit of ring and LC-tank DCOs are comparable and respectively equal to –140.61 dBc/Hz and –136.88 dBc/Hz. It shows, that both DCOs can be used in modern systems for appropriate applications. Main applications of LC-tank DCO are high-speed systems, where high frequency is needed, while in low-cost, low-power systems ring DCO is more suitable.

CNTFET Technology for RF Applications: Review and Future Perspective

RF CNTFETs are one of the most promising devices for surpassing incumbent RF-CMOS technology in the near future. Experimental proof of concept that outperformed Si CMOS at the 130 nm technology has already been achieved with a vast potential for improvements. This review compiles and compares the different CNT integration technologies, the achieved RF results as well as demonstrated RF circuits. Moreover, it suggests approaches to enhance the RF performance of CNTFETs further to allow more profound CNTFET based systems e.g., on flexible substrates, highly dense 3D stacks, heterogeneously combined with incumbent technologies or an all-CNT system on a chip.

Analysis and Design of a Low Noise Shunt-Shunt CMOS Transimpedance Amplifier for 10 Gbps Optoelectronic Receivers

This article presents a complete design flow of a low noise transimpedance amplifier for 10 Gbps optoelectronic receivers. The proposed topology is based on the shunt-shunt structure with negative feedback. A set of equations was deduced from the frequency analysis and noise analysis. An optimization algorithm is proposed in order to maximize the bandwidth and improve the noise performance simultaneously. Experimental results shown a 51 dBΩ transimpedance gain, a 10.54 Ghz bandwidth and an input referred current noise equal to 6.8, the lowest one between other state-of-art designs. The circuit was manufactured in 130 nm RF CMOS technology.

TWO STAGE ON OFF KEYING CLASS A RF POWER AMPLIFIER IN 0.18μm CMOS TECHNOLOGY

A novel architecture for the On Off Keying (OOK) modulator with high gain and high data rate power amplifier (PA) operating at 11.6 GHz IBM 0.18-µm RF CMOS technology is presented for a X-band passive RFID tag. Currently used low frequency switching techniques such as multiplexers were not functioning in the high frequency X-band architectures. In this novel approach OOK modulator with power amplifier, a CMOS switch was used to transmit ‘1’ and ‘0’ coming from the digital signal unlike in the existing low frequency architectures. Both the load and driver in this proposed PA were class A operation supplied by a single ended 1.83V source. The important design considerations include output power, 1 dB compression point and linearity. The fabricated results of the amplifier have a 1 dB compression point of 1.2 dBm and input power of 5.19 dBm at 9.2 GHz.

C3S–QVCO: A low phase noise low power super–harmonic coupling QVCO with cross–connected common–source nodes

In this paper, a novel passive super–harmonic coupling QVCO is presented. The coupling is achieved by Cross–Connecting the top and bottom Common–Source nodes in the complementary (current reuse) LC Cross–Coupled oscillator topology, and therefore, the circuit is named as C3S–QVCO. Unlike the transformer coupling QVCO (TC–QVCO), as the typical super–harmonic coupling technique, the die area is not increased. Also, in the proposed QVCO, neither additional power consumption nor additional noise generator component is required, for quadrature operation. Therefore, the proposed QVCO has a good power consumption performance. The proposed method is evaluated theoretically and analytically, and it is proved that the proposed method is capable of generating multi–phase outputs. The proposed QVCO is designed in a 0.18 ​μm RF–CMOS technology with a power supply of 1.8 ​V, the current consumption of 6.25 ​mA, and the tuning range of 3.75–3.95 ​GHz (5.3%). Post layout simulation result shows −129 ​dBc/Hz, and 190 ​dB phase noise and FOM for the proposed QVCO at 1 ​MHz offset from the 3.75 ​GHz frequency. The proposed QVCO presents 6 ​dB phase noise improvement compared to parallel (P)–QVCO and also demonstrates similar phase noise performance to that of the TC–QVCO, with the same power consumption. Maximum phase/amplitude errors of the proposed QVCO for a 1% mismatch in the oscillator’s tank capacitors are 0.72°/2 ​mV, in the whole tuning range. Those are 0.77°/7.3 ​mV for the P–QVCO and 1.3°/2.3 ​mV for the TC–QVCO.

Low‐power inductorless wideband SFBB balun low noise amplifier with noise reduction and third‐order transconductance optimization

AbstractThis article presents an inductorless wideband balun low noise amplifier (LNA), which uses noise reduction and linearity optimization techniques at low supply voltages. The proposed self forward body biased LNA uses inverter type amplifier structure as input stage for impedance matching while output stages are noise reduction stages, which partially cancel the noise of the input stage. In addition to noise reduction, transistors are biased near‐zero third‐order transconductance region to maximize third‐order input‐referred intercept point (IIP3) performance at low supply voltages. The LNA, implemented in 180 nm RFCMOS technology, is evaluated at 1 and 0.9 V supply voltages to show low voltage operation. It shows a maximum voltage gain of 19.7 dB with a minimum noise figure of 2.7 dB and a maximum 3‐dB bandwidth that spans from 300 MHz to 1.83 GHz. The minimum achieved IIP3 at 0.9 V supply voltage is −1.7 dBm. The circuit draws a maximum current of 10.36 mA from 1 V power supply and occupies an area of 0.08 mm2.