RF SOI Research Articles

Utilizing Symmetric BSIM-SOI SPICE Model for Dynamically Depleted RF SOI T/R Switches and Logic Circuits

Utilizing Symmetric BSIM-SOI SPICE Model for Dynamically Depleted RF SOI T/R Switches and Logic Circuits

RF Performance and TID Hardness Trade-offs in Annular 45-nm RF SOI CMOS Devices

RF Performance and TID Hardness Trade-offs in Annular 45-nm RF SOI CMOS Devices

High-Powered RF SOI Switch With Fast Switching Time for TDD Mobile Applications

This paper presents a fast switching and high-powered single-pole double-throw (SPDT) switch for RF switch circuits, such as TRx antenna switches and frequency band (or operation mode) selection switches in mobile handset applications. For fast switching time and performances of the RF switch, we proposed a novel method that can “selectively” control the impedance of a gate biasing circuit (“high” or “low” impedance). The proposed SPDT switch use the low impedance of the gate biasing circuit for fast switching time and use the high impedance of the gate biasing circuit to avoid the degradation of the insertion loss and harmonics. The proposed SPDT switch has no additional bias and no large payment for size consumption. According to measurement results, the turn-on switching time of the proposed SPDT switch was <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.35~\mu \text{s}$ </tex-math></inline-formula> (at 2 GHz). The insertion loss, isolation, and return loss at 2 GHz were 0.16 dB, 47.1 dB, and 24 dB respectively. 2nd and 3rd harmonic levels at 25 dBm input power at 2 GHz were −88.7 dBm and −78.9 dBm, respectively. Power handling capability was 39.5 dBm of input power at 2 GHz. The designed SPDT switch was implemented in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> partially depleted silicon-on-insulator (PD-SOI) process.

On the Design Principles of 3-D RESURF-Enhanced RF SOI LDMOSFETs: Gate Geometry Optimization and Rescaling

Gate aspect-ratio rescaling is correlated with improved electrical performance of the 3-D-reduced-surface-field (RESURF)-enhanced 80-V radio frequency (RF) silicon-on-insulator (SOI) laterally double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) possessing a 22.86-MW <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{{-2{}}}$ </tex-math></inline-formula> unipolar figure of merit (FOM). The gate layout optimized by alignment with the n-stripe facilitates ideal charge transport into the drift region, orchestrating superior current handling capability, transconductance, and RF gain characteristics at a high gate bias for large-signal operation to bolster a 32-fold increase in transition frequency and at least one order of magnitude rise in maximum frequency of oscillation over that of the classical device at a comparable voltage rating.

Broadband, High-Linearity Switches for Millimeter-Wave Mixers Using Scaled SOI CMOS

This work demonstrates new circuit techniques in distributed-stacked-complimentary (DiSCo) switches that enable picosecond switching speed in RF CMOS SOI switches. By using series-stacked devices with optimized gate impedance and voltage swing, both high linearity and fast switching are possible. A theoretical analysis and design framework has been developed and verified through simulation and measurement through two broadband, high-linearity passive mixer designs, one optimized for linearity and the other for bandwidth, using a 45-nm SOI CMOS process. The mixers achieve P1dBs of 16-22 dBm with IIP3s of 25-34 dBm across a bandwidth from 1 GHz up to 30 GHz. This performance exceeds prior SOI RF and microwave mixer performance by more than an order of magnitude and is comparable to III-V device technologies. The mixers include integrated local oscillator (LO) driving amplifiers for high efficiency operation and low total power consumption. DC power consumption ranges from 250 mW to 1 W for the LO driver. The integrated LO drivers demonstrate a pathway to on-chip LO generation with simplified matching to maximize LO power delivered to the input of the switch.

Analysis and Design of a Broadband Output Stage With Current-Reuse and a Low Insertion-Loss Bypass Mode for CMOS RF Front-End LNAs

This article presents a comprehensive analysis of a novel broadband output stage for external RF front-end low-noise amplifiers (eLNAs). Both variants of the output stage are manufactured using a 130nm bulk CMOS technology. They utilize a common-drain output stage with current-reuse topology, switchable resistive feedback, and source-degeneration. Also, a novel inductor-less low insertion-loss bypass mode is implemented for enhanced bypass functionality. The LNAs are implemented with 4 gain modes achieving excellent RF performance in all possible mobile communication scenarios. Furthermore, an auxiliary linearization circuitry (NMOS IMD sinker) is implemented for variant β to improve linearity performance in low gain mode. Besides, the LNAs support all frequency bands between 1.4GHz and 2.7GHz by only changing the external matching component, allowing easy adaption to different frequency bands. Two offered solutions are realized with a die size of only 0.16mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.11mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. The power consumption is 6.0mW in high gain, 3.6mW in low gain and active-bypass and 0.12mW in bypass mode using a supply voltage of 1.2V. Moreover, a 5.15GHz LNA with high-Q on-chip matching and the broadband output stage is realized and manufactured using a 60nm RF SOI technology. A NF performance of only 1.15dB is achieved consuming only 6.0mW power.

Continuous True-Time Delay Phase Shifter Using Distributed Inductive and Capacitive Miller Effect

A new true-time delay phase shifter concept is proposed exploiting the distributed Miller effect in coupled transmission lines. Simultaneous change in Miller capacitance and inductance controlled by a single analog voltage changes the propagation delay of a transmission line with constant input impedance and insertion loss. The true-time delay line feature of the proposed architecture accommodates a wide bandwidth signal without group delay distortion. A theoretical framework for understanding Miller inductance from voltage and current duality and the distributed Miller effect using coupled wave equations is presented. As a proof of concept, a four-stage tunable delay line with a high-speed phase modulation capability was fabricated in a 45-nm RF SOI CMOS process and occupies an active area of 0.28 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured IC demonstrates a broadband tunable true-time delay with a measured group delay tuning range of 18 ± 1 ps from 11 to 24 GHz. The measured phase shift ranges are 173° and 182° with insertion losses of 10.6 ± 0.7 dB and 11.6 ± 1 dB at 28 and 30 GHz, respectively. The measured dc power consumption is 22 mW from a 1.2-V supply.

High-performance RF Switch in 0.13 μm RF SOI process

A high-performance single-pole single-throw (SPST) RF switch for mobile phone RF front-end modules (FEMs) was designed and characterized in a 0.13 μm partially depleted silicon-on-insulator (PD SOI) process. In this paper, the traditional series-shunt configuration design was improved by introducing a suitably large DC bias resistor and leakage-preventing PMOS, together with the floating body technique. The performance of the RF switch is greatly improved. Furthermore, a new Ron × Coff testing method is also proposed. The size of this SPST RF switch is 0.2 mm2. This switch can be widely used for present 4G and forthcoming 5G mobile phone FEMs.

Ultra Low-Loss Si Substrate for On-Chip UWB GHz Antennas

In this paper, measurements and simulations of miniature monopole antennas for ultra-wideband (UWB) GHz intra- and inter-chips communication and biomedical applications are presented. Folded designs on four substrates are studied: 1) standard bulk; 2) high-resistivity bulk; 3) ultra low-loss radiofrequency silicon-on-insulator (RF SOI); and 4) quartz. Among the Si-based substrates, RF SOI with its trap-rich sublayer demonstrates the best performances with the lowest RF power losses and centimetric transmission distance between antennas. Transmitted power between two antennas was measured from 0.01 to 20 GHz. Using substrate characterization of resistivity, permittivity, and loss tangent based on measured coplanar waveguide lines on the same substrates, good agreement is obtained between the return losses of simulated antennas on each substrate and numerical solutions, confirming the impact of the substrate properties. An antenna bandwidth of 680 MHz is demonstrated at 6.0 GHz meeting the criterion for UWB radio communications in the 6–10 GHz band.

(Invited) SOI Wafer Technology for Advanced Mos Applications

Emerging microelectronic applications such as Internet-Of-Things (IOT) or mixed signal processing utilize fully depleted MOSFETs built on SOI wafers. Advanced FD devices such as planar MOSFETs with back gate biasing require wafers with thin Si top layer as well as ultra thin BOX layer. To sustain good electrostatic control of the channel and to keep back-gate voltages reasonably low, top Si layer thickness has to be in the 5-10 nm range and BOX thickness needs to be less than 20 nm. The SmartCutTM process is the only technology that allows transferring extremely thin layers of silicon on a wide range of handling substrates with industrial quality. As threshold voltage of FD SOI transistor depends on the thickness of Si layer, the thickness has to be controlled within extremely tight tolerance, typically + /- 5A in full range of spatial frequencies spanning from 10 nm till 300 mm [1]. This creates challenge not only for manufacturing technology, but requires development of new thickness metrology. Introduction of differential reflection microscopy (DRM) [2] allows in-line SOI thickness control in wide range of spatial frequencies with unprecedented throughput and precision. The principles and main applications of DRM will be discussed in the presentation. The key process steps with their influence on specific spatial frequencies are identified. One of the main contributors to mid range frequency (in mm range) thickness variation is the interaction of propagating fracture front with acoustic waves emitted by itself. The experimental verification of this mechanism as well as the results of numerical simulations will be presented. Another critical process in SOI technology is reduction of high frequency thickness variations during finishing steps. Possibilities of using pure surface diffusion as well as chemically enhanced high temperature smoothing will be demonstrated. It will be shown that during high temperature annealing in neutral atmosphere Si surface evolution can be described by Mullings-Herring equation with two extra stochastic terms, responsible for conservative and non-conservative noise, while addition of HCl to the annealing atmosphere changes surface behavior to surface relaxation described by the Edwards-Wilkinson model. General linear 4th order surface development model is proposed covering both mechanisms. Material parameters for the model are determined experimentally in the case of HCl(<1%)/H2 etching of silicon. For some advanced applications base wafer of SOI structure can play functional role in the final device, not limited to a mechanical support. One of such examples is RF SOI substrates specifically designed for RF analog applications, such as front end RF modules in smartphones. Introduction of thermally stable layer with high density of carrier traps between BOX layer and high resistivity Si substrate significantly improves high frequency electrical parameters of the devices built on such substrates [3]. Insertion loss, second harmonic generation of coplanar waveguides as well as quality factors of inductors are such main parameters. Empirical model is presented which allows prediction of the results of RF measurements from simple SRP data.

A 2.33-GHz, −133-dBc/Hz, and Eight-Phase Oscillator With Dual Tanks and Adaptive Feedback

This paper presents a multiphase clock generation technique, which employs coupled oscillators and the capacitive-coupling mechanism to achieve both low-power and low-noise characteristics. An oscillator core equipped with both dual tanks and the adaptive feedback technique is proposed. To verify the concept, a four-core coupled oscillator is implemented, and an analytical model on its phase noise performance is presented using the generalized Adler’s equation. The proposed four-core coupled oscillator is fabricated in a 130-nm CMOS RF SOI process. It achieves measured phase noise of −133 dBc/Hz at 1-MHz offset from 2.33 GHz. The current consumption for each oscillator core is 10 mA from a 1–V supply voltage. The figure of merit (FoM) of the eight-phase oscillator is 184.3 dBc/Hz; resulting in a per-phase FoM of 193.3 dBc/Hz.

High Resistivity SOI RF CMOS 인덕터의 주파수 종속 Quality Factor 모델링

High Resistivity SOI RF CMOS 인덕터의 주파수 종속 Quality Factor 모델링

(Invited) VLSI-CMOS Device Technology Scaling Landscape Based on Fully-Depleted SOI and 3D-FinFET Technologies for the Internet of Everything Era

Smart and innovative products are using the convergence of ubiquitous sensing and the communication by the internet. The so called Internet of Things/Everything (IoT/IoE) emerges from the traditional computing and mobile market and impacts every era in humans’ lives. Moore’s Law is the driver of these innovations in increasing component integration on SoC’s to deliver the right combination of performance, power, and cost to match the appropriated application. To continue to create compelling products, it will increasingly require all advancements and differentiations, more directly linking the CMOS-VLSI scaling to the integrated circuits; in an era where future systems may be different than the computers we are familiar with. A large variety of emerged technology concepts especially in the communication and sensor area as well as non-volatile memories will converge with the well-established VLSI-CMOS technology. The main requirements on the single semiconductor device and technologies are lowest leakage at lowest voltage operation at the minimum cost. Differentiated technologies such as 22nm and 12nm Fully Depleted Silicon on Insulator (FDSOI), common partially depleted SOI (PDSOI) RF as well as novel non-volatile memory concepts are entering the markets. Furthermore, SoC innovations will focus on 3D multi-die package integrations on system level to growth technologies into the Internet of Everything area. Planar CMOS devices especially in 28nm and 20nm are currently the mostly used technologies for mass production microprocessors and SoC’s since it’s at an optimized spot of cost and performance. Over the last decades new processing techniques as well as new materials have been introduced such as strained Si, high-k metal gate and ultra-low-k. With the non-manufacturable arrival of EUV lithography integration techniques such as double and quadruple patterning, self aligned contacts; air-gap interconnects as well as new materials are needed for VLSI technologies of 7nm and beyond. 3D FinFET devices as well as new device architectures are required to continue an over-scaling in order to maintain the historical Moore’s Law to overcome the increased cost per gate. Simultaneously, the effort on variation reduction, performance and yield improvements increases exponentially for the design and manufacturing community. To keep pace with the technology over-scaling advanced techniques and solutions on the design and process integration as well as manufacturing processes are necessary. Reducing all parasitic resistances and capacitances is key for technologies below 7nm to gain in further SoC scaling while maintaining its performance level. The inflection on the cost per gate trend can be intercepted by differentiated technologies that serve markets for the respective applications such as 22nm and 12nm FDSOI. Those technologies offer a wide variety and individualism for designs to serve the IoT/E era perfectly. The FDSOI technology is a real independent multi-gate technology which can span an infinite VTH space for any circuit design. In addition it’s well suited for low and lowest power applications as well as RF, mmWave, analog and mixed Signal SOC’s. Since it’s a planer technology, process and technology elements from previous nodes can be transformed into this novel architecture. With its diffusion less concept scaling is possible down to the 12nm technology node while maintaining the lowest cost trend by saving up to 30% fewer mask steps. The performance produces NFET (PFET) drive currents of up to 910μA/µm (856μA/µm) at 0.8V and 100nA/µm IOFF. For ultra-low power applications, it offers low-voltage operation down to 0.4V Vmin. Ultra-low leakage devices serve up to 1pA/µm IOFF and body-biasing can be used to actively trade-off power and performance. RF/Analog characteristics are achieved including high fT/fMAX of 375GHz/290GHz and 260GHz/250GHz for NFET and PFET, respectively. The high fMAX extends the capabilities to 5G and mmWave (>24GHz) RF applications. Implementing an increased amount of sub-systems like graphic, video, TV, RF applications, sensor interfaces etc. challenges occur on I/O interface components and sub-system scaling. What once was 5-15% of a SoC die area is rapidly increased to 30-40% as the digital side over-scales in attempt to keep costs in line with Moore’s law. New 3D IC stacking technology concepts being introduced, which need to maintain the over-scaling and keeping the overall cost scaling on Moore’s Law historical trend line. Cost scaling can be enhanced with advanced methods on direct wafer boding, 3D-TSV or inductive coupling, which will come at a total power tradeoff, as the total combined die area will increase compared to a monolithic die. Continues innovation in area over-scaling and derivative technology approaches such as FDSOI will keep the current SoC’s scaling near the historic Moore’s Law trend to serve appropriate applications optimized in performance, power, and cost.

Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure

This work presents a model parameter extraction method based on four-port network for RF SOI MOSFET modeling. The gate, drain, source and body terminals are served as four separate ports. Four-port measurement simplifies the determination of small-signal equivalent circuit model elements such as parameters related to the body terminal which become clear in the equivalent circuit analysis. The extraction method of the RF SOI MOSFET extrinsic parasitic elements was also presented. The accuracy of the model extraction was verified by measurement and simulation from 100 MHz to 20 GHz.

A direct method to extract extrinsic capacitances of rf SOI MOSFETs using common source‐body and gate‐body configurations

ABSTRACTA direct extraction method is newly proposed to determine all extrinsic capacitances including the drain‐source coupling capacitance in a buried oxide layer of RF SOI MOSFETs. This new method is based on Y‐parameter equations derived from two “off” state equivalent circuits under common source‐body and gate‐body configurations. Using this method, the gate voltage‐dependent extrinsic capacitance data are extracted and small‐signal equivalent circuit modeling is accurately performed. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2851–2853, 2016

An improved model for substrate in RF SOI MOSFET varactor

SummaryA simple small‐signal equivalent circuit based on the physical structure of silicon‐on‐insulator metal–oxide–semiconductor field‐effect transistor varactor for substrate loss effects is presented in this paper. The model includes a BSIMSOI charge formulation and physical geometry and process parameter based on parasitic modeling. Key device performances of capacitance and quality factor are validated over voltage, frequency, and geometry. The model, implemented in Verilog‐A, provides robust and accurate radiofrequency simulation of metal–oxide–semiconductor varactor. Copyright © 2016 John Wiley &amp; Sons, Ltd.

A CMOS power amplifier using split input and output transformers to minimize its chip area

In this study, we propose a layout technique to reduce the chip area of differential RF CMOS power amplifiers in which input and output transformers are utilized as input and output baluns. To minimize the chip area of the CMOS power amplifier, we split a conventional spiral transformer into two identical parts, thereby making full use of the wasted area in the conventional power amplifier. Using the proposed split transformers in the input and output transformers, we successfully reduce the chip area of the CMOS power amplifier based on a differential structure. To verify the feasibility of the proposed split cascode structure, we designed a 2.4-GHz CMOS power amplifier using a 180-nm SOI RF CMOS process. With an IEEE 802.11n WLAN modulated signal, we obtain a maximum output power of 9.73 dBm. From the measured results, we verify the feasibility of the proposed split transformer structure for RF CMOS power amplifier applications. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1443–1446, 2016

High Resistivity SOI RF CMOS 대칭형 인덕터 모델링을 위한 개선된 Optimization 방법 연구

High Resistivity SOI RF CMOS 대칭형 인덕터 모델링을 위한 개선된 Optimization 방법 연구

Irradiation and Temperature Effects for a 32 nm RF Silicon-on-Insulator CMOS Process

The impacts of total ionizing dose (TID), temperature and RF stress on the DC and RF performance of a commercial 32 nm RF silicon-on-insulator CMOS technology are presented. Temperature dependence is the overwhelmingly dominant single factor affecting the DC and RF performance, with the combined effects of elevated temperature and TID showing the most pronounced degradation. The most significant effect due to TID is an increase in off-state leakage current. Key DC and RF parameters of this 32 nm RF process degrade less than those of an otherwise similar 45 nm RF SOI CMOS process. The implications of the combined TID and temperature response are discussed for low-power RF design.

A Novel RF SOI LDMOS with a Raised Drift Region

In this paper, we propose a novel RF SOI LDMOS with a raised drift region (RDR). Using the process simulation and numerical simulation, we investigate deeply on breakdown characteristics and frequency characteristics of this novel device. Compared with the conventional RESURF device, the breakdown voltage and cutoff frequency of the RDR device are increased by 25% and 21%, respectively. The work of this paper has theoretical and practical significations to the research of a new generation of deep sub-micron high-performance radio frequency SOI integrated circuits.