RF ESD Protection Research Articles

A 28 GHz balun‐first LNA with db‐linear 32 db gain range for 5 G applications

AbstractThis letter presents a 28 GHz balun‐first low noise amplifier (LNA) featuring a wide dB‐linear variable gain range. The architecture of LNA includes three‐stage cascode amplifiers. An integrated balun at the input stage provides RF ESD protection and converts a single‐ended signal to a differential one (S‐to‐D). A transformer‐based dual‐resonant matching network is designed and analyzed to achieve wideband performance. To realize a continuous dB‐linear variable gain range and consistent input/output matching, gain control is implemented in the second stage using a 5‐bit digital‐to‐analog converter (DAC) for a 32 dB gain range. The DAC can generate a nonlinear analog voltage to control the gate of the common‐gate transistor in the second cascode stage, inversely compensating for the nonlinear gain variations of the cascode amplifier. The LNA is fabricated in 65‐nm CMOS process with a core size of 0.154 mm². Measurement results exhibit a maximum gain of 33.5 dB and a minimum noise figure (NF) of 3.65 dB with a 3‐dB bandwidth of 23–29.5 GHz. The measured variable gain range is approximately 32 dB across 32 different gain states, with a linear gain step of ~1 dB per state and an IP1dB ranging from −6.5 dBm to −35.25 dBm. The power consumption is 35.4–48 mW from a 1.2 V supply voltage.

New triggering-speed-characterization method for diode-triggered SCR using TLP

The key parameters in the optimization of the Diode Triggered Silicon-Controlled Rectifier (DTSCR) as a RF ESD protection, are the turn-on time and the trigger-voltage overshoots seen before the SCR turns on, during very fast ESD transients [1]. But at this time, there is no normalized method to evaluate and report the ESD device turn-on speed [2]. Such a method would be required to effectively compare device performance. In this work a new method, based on stored-charge, is investigated to characterize the triggering speed of DTSCR using Transmission Line Pulsing (TLP) measurements.

Correction to “Improved Low-Voltage-Triggered SCR Structure for RF-ESD Protection” [Aug 13 1050-1052

There is an error in Fig. 1 in the above-named letter [ibid., vol. 34, no. 8, pp. 1050-1052, Aug. 2013]. The corrected figure is published here.

Improved Low-Voltage-Triggered SCR Structure for RF-ESD Protection

An improved low-voltage-triggered silicon-controlled rectifier is proposed for on-chip electrostatic discharge (ESD) protection in a 65-nm radio frequency CMOS. The experimental results show that it has a very low intrinsic capacitance of 18 fF at zero bias, a low and tunable trigger voltage in the range of 2.2-4.5 V, a low leakage current of 0.3 nA, and a low overshoot voltage under very fast ESD pulse. It achieves a 1.9-A failure current with only 50×9-μm2 layout area.

A Low Power 77 GHz Low Noise Amplifier With an Area Efficient RF-ESD Protection in 65 nm CMOS

An area efficient electrostatic discharge (ESD) protection structure is presented to protect the RF input PAD of a 77 GHz low noise amplifier in a 65 nm CMOS process. The results show a measured small signal gain of 10.5 dB at 77 GHz with 37 mW dc power consumption. The measured noise figure at 77 GHz is 7.8 dB. The proposed RF-ESD protection co-design using an inductive cancellation method can handle transmission line pulse ESD currents up to more than 2.7 A without RF performance degradation, which corresponds to an equivalent 4.05 kV voltage level of the human body model. The occupied area by the ESD device is only 0.01 , reducing cost and making it suitable for highly integrated mmW receivers.

RF ESD protection strategies: Codesign vs. low- C protection

The present work is focussed on the trade-off between conventional RF ESD protection concepts optimized in terms of capacitive load and the frequently discussed RF ESD codesign idea with ESD protection skilfully integrated into RF circuit design. A narrow and a broadband RF test circuit were developed to put the benchmark on a firm basis. RF and ESD experiments are discussed, showing where the higher effort for the codesign approach starts to pay off.