A Low Power 77 GHz Low Noise Amplifier With an Area Efficient RF-ESD Protection in 65 nm CMOS

Abstract

An area efficient electrostatic discharge (ESD) protection structure is presented to protect the RF input PAD of a 77 GHz low noise amplifier in a 65 nm CMOS process. The results show a measured small signal gain of 10.5 dB at 77 GHz with 37 mW dc power consumption. The measured noise figure at 77 GHz is 7.8 dB. The proposed RF-ESD protection co-design using an inductive cancellation method can handle transmission line pulse ESD currents up to more than 2.7 A without RF performance degradation, which corresponds to an equivalent 4.05 kV voltage level of the human body model. The occupied area by the ESD device is only 0.01 , reducing cost and making it suitable for highly integrated mmW receivers.