RF Analog Applications Research Articles

Vertical Dopingless Dual-Gate Junctionless FET for Digital and RF Analog Applications

Vertical Dopingless Dual-Gate Junctionless FET for Digital and RF Analog Applications

(Invited) SOI Wafer Technology for Advanced Mos Applications

Emerging microelectronic applications such as Internet-Of-Things (IOT) or mixed signal processing utilize fully depleted MOSFETs built on SOI wafers. Advanced FD devices such as planar MOSFETs with back gate biasing require wafers with thin Si top layer as well as ultra thin BOX layer. To sustain good electrostatic control of the channel and to keep back-gate voltages reasonably low, top Si layer thickness has to be in the 5-10 nm range and BOX thickness needs to be less than 20 nm. The SmartCutTM process is the only technology that allows transferring extremely thin layers of silicon on a wide range of handling substrates with industrial quality. As threshold voltage of FD SOI transistor depends on the thickness of Si layer, the thickness has to be controlled within extremely tight tolerance, typically + /- 5A in full range of spatial frequencies spanning from 10 nm till 300 mm [1]. This creates challenge not only for manufacturing technology, but requires development of new thickness metrology. Introduction of differential reflection microscopy (DRM) [2] allows in-line SOI thickness control in wide range of spatial frequencies with unprecedented throughput and precision. The principles and main applications of DRM will be discussed in the presentation. The key process steps with their influence on specific spatial frequencies are identified. One of the main contributors to mid range frequency (in mm range) thickness variation is the interaction of propagating fracture front with acoustic waves emitted by itself. The experimental verification of this mechanism as well as the results of numerical simulations will be presented. Another critical process in SOI technology is reduction of high frequency thickness variations during finishing steps. Possibilities of using pure surface diffusion as well as chemically enhanced high temperature smoothing will be demonstrated. It will be shown that during high temperature annealing in neutral atmosphere Si surface evolution can be described by Mullings-Herring equation with two extra stochastic terms, responsible for conservative and non-conservative noise, while addition of HCl to the annealing atmosphere changes surface behavior to surface relaxation described by the Edwards-Wilkinson model. General linear 4th order surface development model is proposed covering both mechanisms. Material parameters for the model are determined experimentally in the case of HCl(<1%)/H2 etching of silicon. For some advanced applications base wafer of SOI structure can play functional role in the final device, not limited to a mechanical support. One of such examples is RF SOI substrates specifically designed for RF analog applications, such as front end RF modules in smartphones. Introduction of thermally stable layer with high density of carrier traps between BOX layer and high resistivity Si substrate significantly improves high frequency electrical parameters of the devices built on such substrates [3]. Insertion loss, second harmonic generation of coplanar waveguides as well as quality factors of inductors are such main parameters. Empirical model is presented which allows prediction of the results of RF measurements from simple SRP data.

Electronic Transport in Laterally Asymmetric Channel MOSFET for RF Analog Applications

In this paper, an ensemble Monte Carlo investigation of the static and dynamic performances in the high-frequency domain of laterally asymmetric channel (LAC) bulk metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. A detailed comparison with a homogeneously doped bulk device is also included. The results presented show that the use of an asymmetric doping within the channel enhances nonequilibrium features as velocity overshoot, thus significantly improving the transconductance of the device. The gradual variation of doping is also responsible for a modification of the electrostatic conditions and the inversion charge profiles, provoking the reduction of the gate-to-source capacitance, a minor influence of surface scattering, reduced transit times, and higher mean free paths. A noticeable enhancement (as compared to a conventional device) in the RF and microwave frequency range of the dynamic performance of the transistors is also evidenced. This is mainly due to a better transconductance-to-current ratio, Early voltage, and open-loop gain, which are the results of the improvement of the charge transport conditions in the device at a microscopic level. Therefore, LAC MOSFETs can be a viable option to enhance the figures of merit of bulk silicon technology for high-frequency analog applications.

Frequency Dependence of Measured Metal Oxide Semiconductor Field-Effect Transistor Distortion Characteristic

Non-linearity of metal oxide semiconductor field-effect transistor (MOSFET) characteristics induces harmonic distortions, which causes serious problems for RF analog applications. Features of the harmonic distortions are investigated experimentally under high frequency operations. Comparison of measured harmonic distortions with inter-modulation distortions concludes that the harmonic distortions are frequency dependent under high frequency operations. A reason for this is enhanced contribution of the displacement, which is originally frequency dependent.

A novel lateral bipolar transistor with 67 GHz f/sub max/ on thin-film SOI for RF analog applications

In this paper, a novel lateral bipolar transistor on thin film silicon-on-insulator (SOI) is presented. With a small emitter size of 0.12/spl times/3.0 /spl mu/m/sup 2/, low base resistance of 270 /spl Omega/ due to a novel Co silicided base electrode and low base-collector parasitic capacitances of 1.4 fF due to SOI material, it achieves the highest f/sub max/ of 67 GHz among SOI bipolar transistors. Also, the low emitter-base capacitance of 1.5 fF and the low collector-substrate capacitance of 2.5 fF are realized. The transistor has a simple structure, which is fabricated with simplified processes without any new sophisticated technologies, excluding trench isolation and epitaxial base used in current bipolar transistors. This can lower the fabrication cost of transistors. We have demonstrated the possibility of lateral bipolar transistor on thin film SOI as next-generation device for RF analog applications.

An 0.18-μm CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs

An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V/sub th/ for RF analog circuits. The zero-volt-V/sub th/ MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750/spl deg/C, the film quality is as good as the bulk silicon because high pre-heating temperature (940/spl deg/C for 30 s) is used in H/sub 2/ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ values than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications.