Reversible Counter Research Articles

Reversible Computations of One-Way Counter Automata

Deterministic one-way time-bounded multi-counter automata are studied with respect to their ability to perform reversible computations, which means that the automata are also backward deterministic and, thus, are able to uniquely step the computation back and forth. We study the computational capacity of such devices and obtain separation results between irreversible and reversible k-counter automata for polynomial and superpolynomial time. For polynomial time and exponential time we obtain moreover infinite and tight hierarchies with respect to the number of counters. These hierarchies are shown with Kolmogorov complexity and incompressibility arguments. In this way, on passing we can prove these hierarchies also for ordinary counter automata. This improves the known hierarchies for ordinary counter automata in the sense that we consider here a weaker acceptance condition. Then, it turns out that k +1 reversible counters are not better than k ordinary counters and vice versa. Finally, almost all usually studied decidability questions turn out to be undecidable and not even semidecidable for reversible multi-counter automata, if at least two counters are provided. In case of reversible one-counter automata, it is possible to show that the inclusion problem is also not even semidecidable.

Reversible Computations of One-Way Counter Automata

Deterministic one-way time-bounded multi-counter automata are studied with respect to their ability to perform reversible computations, which means that the automata are also backward deterministic and, thus, are able to uniquely step the computation back and forth. We study the computational capacity of such devices and obtain separation results between irreversible and reversible k-counter automata for superpolynomial time. For exponential time we obtain moreover an infinite and tight hierarchy with respect to the number of counters. This hierarchy is shown with Kolmogorov complexity and incompressibility arguments. In this way, on passing we can prove this hierarchy also for ordinary counter automata. This improves the known hierarchy for ordinary counter automata in the sense that here we consider a weaker acceptance condition. Then, it turns out that k+1 reversible counters are not better than k ordinary counters and vice versa. Finally, almost all usually studied decidability questions turn out to be undecidable and not even semidecidable for reversible multi-counter automata, if at least two counters are provided.

Design and Development of 4-Bit Gray Code Counter Circuit Using Reversible Logic Gate

Aim: This paper proposed the design and development of 4-Bit Gray Code Counter Circuit Using Reversible Logic Gate. Methods: The 4-Bit Gray Code Counter Circuit can be design using SAM gate, Feynman gate (FG), double Feynman gate (DFG) and NOT gate. The proposed circuit is the combined application of 4-bit binary asynchronous counter and 4-bit binary to gray code converter circuit. Results: The proposed gray code counter is designed using four no. of SAM gate, three no. of DFG, one FG and seven reversible NOT gate. The QC, GO and CI of proposed circuit are correspondingly 30, 4 and 7. Conclusion: The novel reversible gray code counter have been designed using existing reversible logic gate. The proposed gray code counter is designed using four no. of SAM gate, three no. of DFG, one FG and seven reversible NOT gate. The QC, GO and CI of proposed circuit are correspondingly 30, 4 and 7.

Optimized Design of a Converter Decimal to BCD Encoder and a Reversible 4-bit Controlled Up/Down Synchronous Counter

The field of quantum computing, reversible logic, and nanotechnology have earned much attention from researchers in recent years due to their low power dissipation. Quantum computing has been a guiding light for nanotechnology, optical computing of information, low power CMOS design, computer science. Moreover, the dissipation of energy in the field combina-torial logic circuits becomes one of the most important aspects to be avoided. This problem is remedied by a reversible logic favoring the reproduction of inputs to outputs, which is due to the absence of unused bits. Every bit of information not used generates a loss of information causing a loss of energy under the form of heat, the reversible logic leads to zero heat dissipation. Among the components affected by reversible logic are binary reversible counter and converter from decimal to BCD encoder(D2BE) which are considered essential elements. This article will propose an optimized reversible design of a converter from decimal to BCD encoder (D2BE) and an optimized design of reversible Binary counter with up/ down. Our designs show an improvement compared to previous works by replacing some reversible gates with others while keeping the same functionality and improving performance criteria in terms of the number of gates, garbage outputs, constant inputs, quantum cost, delay, and Hardware complexity.

Design of synchronous decimal counter using reversible Toffoli–Fredkin Netlist

Investigations in reversible computation have been one of the notable dimensions among the emerging research domains. Reversible circuits promise near-zero heat dissipation resulting in a considerable amount of literary proposals. This article proposes a reversible synchronous decimal counter using Toffoli and Fredkin gates. Decimal counter forms an important Boolean specification as they are used for clock generators, frequency dividers, clock division, integrated oscillation, etc. Although literature witnesses exhaustive research in reversible mod-2/4/8/16 counters, there is a void in the domain of reversible decimal counters. We propose three designs D1, D2, and D3. Design D1 and D2 are synchronous decimal up and down counters, respectively, using Toffoli Netlist. Design D3 is the integration of designs D1 and D2 using the Fredkin Gate array. The proposed designs have been checked using a state-of-the-art optimization algorithm in literature and the results reflect our design to be best optimized. Peer analysis reflects a summary of existing literary proposals exhibiting the uniqueness of the proposed designs.

General Method to Design Reversible Universal n-Bit Up/Down Counters

With the growing trend towards reducing the size of electronic devices, reducing power consumption has become one of the major concerns of circuit designers, and designing reversible circuits is one of the approaches proposed for reducing power consumption. Although several studies have been done in the field of synthesizing combinational reversible circuits, little work has been done for designing reversible sequential circuits. Furthermore, many researches in this context use traditional designs which replace latches, flip-flops and associated combinational gates with their reversible counterparts. This traditional technique is not very promising, because it leads to high quantum cost (QC) and garbage outputs. Recently, researchers have proposed direct design of reversible sequential circuits using Reed Muller expressions to obtain next state output. Since most sequential circuits have multiple outputs, using common product terms between multiple outputs might decrease QC significantly. In this paper, a modular and low QC design for a synchronous reversible [Formula: see text]-bit up/down counter with parallel load capability is presented. In this design, the common terms among multiple outputs are used efficiently, which leads to a low QC for the counter. A general formula to evaluate the QC of our proposed reversible counter is presented. This result shows that in our proposed design by increasing the number of bits of counter ([Formula: see text], the QC increases linearly, while in previous works by increasing the number of bits of counter, the QC increases exponentially.

Low-cost and compact design method for reversible sequential circuits

Reversible logic plays an important role in nanotechnology-based systems; therefore, it has become an interesting topic for many researchers in this field. Although many researchers are investigating techniques to synthesize reversible combinational logic, few are working in the field of reversible sequential logic. The traditional method to design a sequential circuit is a replacement technique. In this technique, in order to design a reversible sequential circuit, all parts of an irreversible design (e.g., latches and flip-flops and associated combinational gates) are replaced by their reversible counter parts, which leads to circuits with high quantum cost. In this paper, we propose a direct and compact design of reversible synchronous sequential circuits. The EXOR of Products of EXOR (EPOE) expressions are applied, to reduce the quantum cost of sequential logic circuits. We present designs for some practical sequential circuits, such as state machines, counters and shift registers. To show the efficiency of the proposed method, we have designed a proof of concept of our designs to design a practical sequential system: a reversible self-controlled serial adder. Our designs considerably reduce performance cost factors: including quantum cost, number of constant inputs or the number of garbage outputs and delay.

The non-central negative binomial distribution: Further properties and applications

The non-central negative binomial distribution is both a mixed and compound Poisson distribution with applications in photon and neural counting, statistical optics, astronomy and a stochastic reversible counter system. In this paper various important probabilistic properties of the non-central negative binomial distribution in practical applications like log-concavity, discrete self-decomposability, unimodality, asymptotic behavior and tail length of the probability distribution have been derived. The construction as a mixed Poisson process by specifying a joint distribution for the inter-arrival times and its application is illustrated by a fit to real life data set.

Designing Nanoscale Counter Using Reversible Gate Based on Quantum-Dot Cellular Automata

Some new technologies such as Quantum-dot Cellular Automata (QCA) is suggested to solve the physical limits of the Complementary Metal-Oxide Semiconductor (CMOS) technology. The QCA as one of the novel technologies at nanoscale has potential applications in future computers. This technology has some advantages such as minimal size, high speed, low latency, and low power consumption. As a result, it is used for creating all varieties of memory. Counter circuits as one of the important circuits in the digital systems are composed of some latches, which are connected to each other in series and actually they count input pulses in the circuit. On the other hand, the reversible computations are very important because of their ability in reducing energy in nanometer circuits. Improving the energy efficiency, increasing the speed of nanometer circuits, increasing the portability of system, making smaller components of the circuit in a nuclear size and reducing the power consumption are considered as the usage of reversible logic. Therefore, this paper aims to design a two-bit reversible counter that is optimized on the basis of QCA using an improved reversible gate. The proposed reversible structure of 2-bit counter can be increased to 3-bit, 4-bit and more. The advantages of the proposed design have been shown using QCADesigner in terms of the delay in comparison with previous circuits.

Novel Designs of Quantum Reversible Counters

Reversible logic, as an interesting and important issue, has been widely used in designing combinational and sequential circuits for low-power and high-speed computation. Though a significant number of works have been done on reversible combinational logic, the realization of reversible sequential circuit is still at premature stage. Reversible counter is not only an important part of the sequential circuit but also an essential part of the quantum circuit system. In this paper, we designed two kinds of novel reversible counters. In order to construct counter, the innovative reversible T Flip-flop Gate (TFG), T Flip-flop block (T_FF) and JK flip-flop block (JK_FF) are proposed. Based on the above blocks and some existing reversible gates, the 4-bit binary-coded decimal (BCD) counter and controlled Up/Down synchronous counter are designed. With the help of Verilog hardware description language (Verilog HDL), these counters above have been modeled and confirmed. According to the simulation results, our circuits’ logic structures are validated. Compared to the existing ones in terms of quantum cost (QC), delay (DL) and garbage outputs (GBO), it can be concluded that our designs perform better than the others. There is no doubt that they can be used as a kind of important storage components to be applied in future low-power computing systems.

Design of a novel quantum reversible ternary up-counter

Reversible logic has been recently considered as an interesting and important issue in designing combinational and sequential circuits. The combination of reversible logic and multi-valued logic can improve power dissipation, time and space utilization rate of designed circuits. Only few works have been reported about sequential reversible circuits and almost there are no paper exhibited about quantum ternary reversible counter. In this paper, first we designed 2-qutrit and 3-qutrit quantum reversible ternary up-counters using quantum ternary reversible T-flip-flop and quantum reversible ternary gates. Then we proposed generalized quantum reversible ternary n-qutrit up-counter. We also introduced a new approach for designing any type of n-qutrit ternary and reversible counter. According to the results, we can conclude that applying second approach quantum reversible ternary up-counter is better than the others.

Design of Reversible Synchronous Sequential Circuits Using Pseudo Reed-Muller Expressions

Reversible logic has become very promising for low-power design using emerging computing technologies. A number of good works have been reported on reversible combinational circuit design. However, only a few works reported on the design of reversible latches and flip-flops on the top of reversible combinational gates and suggested that sequential circuits be built by replacing the latches and flip-flops and associated combinational gates of the traditional irreversible designs by their reversible counter parts. This replacement technique is not very promising, because it leads to high quantum cost and garbage outputs. In this paper, we propose a novel approach of designing synchronous sequential circuits directly from reversible gates using pseudo Reed-Muller expressions representing the state transition and the output functions of the circuit. We present designs of arbitrary synchronous sequential circuit as well as practically important sequential circuits such as counters and registers. It is found that our direct designs save 1.54%-49.09% quantum cost and 51.43%-81.82% garbage outputs than the replacement design approach suggested earlier.

Design of Reversible Counter

This article presents a research work on the design and synthesis of sequential circuits and flip-flops that are available in digital arena; and describes a new synthesis design of reversible counter that is optimized in terms of quantum cost, delay and garbage outputs compared to the existing designs. We proposed a new model of reversible T flip-flop in designing reversible counter

CMOS readout circuit for piezo-resistive accelerometer

A novel low power CMOS interface circuit for piezo-resistive accelerometer is presented, which is based on successive approximation. The interface circuit which can calibrate sensor’s zero offset includes amplifier, accumulator, comparator, bidirectional reversible counter, latch, start control logic, and D/A converter. The power of counter and comparer is cut off by start control logic after auto-zeroing to further reduce power dissipation. When the circuit gain is 500 and the input zero offset is 500 mV, the zero offset is 143.5 mV through the first stage of the interface circuit. Through the second stage of the interface circuit the zero offset is 1.9 mV, therefore, the interface circuit calibrates sensor’s zero offset successfully. The circuit is implemented in 0.5 μm CMOS process, the testing results indicate that the max auto-zeroing voltage is 500 mV, the resolution is 4 mV, and the power consumption is 4.62 mW.

Design of Ternary Clocked Adiabatic Synchronous Reversible Counter

Based on the study of synchronous counter and adiabatic circuits, a new design scheme of ternary adiabatic synchronous reversible counter is proposed. According to the theory of three essential circuit elements, circuit structure of four-bit ternary adiabatic synchronous reversible counter is realized by using NMOS transistors with different thresholds and cross-storage structure and combining with the principle of energy recovery. Computer simulation results indicate that the designed circuits have correct logic function. Compared with traditional CMOS counter, the average power consumption of circuits saves up to 67.5%.

Optical reversible counter

The optical reversible counter for optical computer is developed. It permits integral implementation.

Design of an Intelligent Multi-Gyro Measurement Device

This paper describes the design of an intelligent multi-gyro measurement device to measure and monitor an inertial unit composed of three dynamically tuned gyros (DTGs). A 16-bit microprogrammed control unit is programmed to fulfill the functions of signal processing, logic control and serial communication with a master computer. An FPGA, designed by using Verilog Hardware Description Language, is used to realize high speed 16-bit reversible counters for output pulses of the DTG digital dynamic balance circuits. The count values represent the angular motion of the inertial unit. A stepping electric bridge is employed to measure the resistance of thermal resistors within the gyros in a wide temperature environment. The resistance represents the working temperature of the gyros. An effective calibration method for the bridge is developed to eliminate the resistance measurement error. A test system is established to examine whether the device meets the user requirements. Results of the tests show that the device has a good performance. A trial use has proved that the device is stable and reliable and that it satisfies the demand of the user.

Investigation of Yttrium and Polyvalent Ion Intercalation into Nanocrystalline Vanadium Oxide

The electrochemical reactivity of cations such as and into crystalline materials was investigated. The ionic diffusion constant of and into microcrystalline and nanocrystalline was measured by the galvanostatic intermittent titration technique. The ion diffusion constant into a 500 nm crystalline was found to be approximately two orders of magnitude lower than for the ion. In order to enable practical intercalation of a nanocrystalline was fabricated through a combustion flame synthesis technique. For the first time, reversible electrochemical intercalation of into a host structure was shown to be feasible. An asymmetric hybrid cell configuration was utilized in order to provide a reversible counter electrode during intercalation. Preliminary data indicates can be reversibly intercalated into with apparent gravimetric capacities exceeding that of or over the limited voltage range of 2.5 to 4.2 V The concept of polyvalent intercalation is discussed relative to intercalation, pseudocapacitance, apparent specific capacity, and practical energy storage systems. © 2001 Telcordia Technologies. All rights reserved.

Toward robust integrated circuits: The embryonics approach

The growth and operation of all living beings are directed by the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the design of highly robust integrated circuits, endowed with properties usually associated with the living world: self-repair (cicatrization) and self-replication. The Embryonics architecture is based on four hierarchical levels of organization. (1) The basic primitive of our system is the molecule, a multiplexer-based element of a novel programmable circuit. (2) A finite set of molecules makes up a cell, essentially a small processor with an associated memory. (3) A finite set of cells makes up an organism, an application-specific multiprocessor system. (4) The organism can itself replicate, giving rise to a population of identical organisms. We begin by describing in detail the implementation of an artificial cell characterized by a fixed architecture, showing that multicellular arrays can realize a variety of different organisms, all capable of self-replication and self-repair. In order to allow for a wide range of applications, we then introduce a flexible architecture, realized using a new type of fine-grained field-programmable gate array whose basic element, our molecule, is essentially a programmable multiplexer. We describe the implementation of such a molecule, with built-in self-test, and illustrate its use in realizing two applications: a modulo-4 reversible counter (a unicellular organism) and a timer ( a complex multicellular organism). We describe our ongoing research efforts to meet three challenges: a scientific challenge, that of implementing the original specifications formulated by John von Neumann for the conception of a self-replicating automaton; a technical challenge, that of realizing very robust integrated circuits capable of self-repair and self-replication; and a biological challenge, that of attempting to show that the microscopic architectures of artificial and natural organisms, i.e., their genomes, share common properties.

High-Contrast Electrochromic Polymers from Alkyl-Derivatized Poly(3,4-ethylenedioxythiophenes)

The syntheses of two new derivatives of 3,4-ethylenedioxythiophene (EDOT), specifically 5-octyldioxeno[2,3-c]thiophene (EDOT-C8) (2) and 5-tetradecyldioxeno[2,3-c]thiophene (EDOT-C14) (3), and their polymers are reported in this paper. Cyclic voltammetry of 2 and 3 in 0.1 M TBAP/CH3CN show irreversible monomer oxidation peaks (Ep,m) at 0.89 and 0.93 V, respectively. Multiple scans yield electroactive and conducting polymer films on electrode surfaces. The PEDOT-C8 and PEDOT-C14 formed oxidize with relatively low peak potentials at −0.22 and −0.19 V, respectively, indicating the doped form of the polymer to be quite stable. Both PEDOT-C8 and PEDOT-C14 show two reduction processes with peaks at −0.18 and −0.16 V (Ec2,p) and −0.55 and −0.36 V (Ec1,p) respectively. Optoelectrochemical studies reveal an Eg of 1.75 eV for both polymers. The polymers are electrochromic, relatively transmissive and light gray in the oxidized form, while being opaque and deep purple in the reduced form exhibiting high electrochromic contrasts. Long term switching studies carried out in 0.1 M LiClO4/PC with Li/Li+ as a reversible counter electrode shows that PEDOT, PEDOT-C8, and PEDOT-C14 retained 65%, 50%, and 62% of their electroactivity after 6000, 9000, and 16 000 double switches, respectively.