Reversible Logic Research Articles

The use of reversible logic gates in the design of residue number systems

Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2<sup>k</sup>, 2<sup>p</sup>-1}. Modulo 2<sup>n</sup>-1, 2<sup>n</sup>, and 2<sup>n</sup>+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2<sup>n</sup>-1, 2<sup>n+k</sup>, 2<sup>n</sup>+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.

Quantum Computer-Aided Design Automation

Quantum computing is an essential issue for taking advantage of quantum properties in real-world applications. Realizing quantum computing with a corresponding quantum circuit is a critical step. This study introduces the AngelQ system, which provides quantum computing-as-a-service (QCaaS) for the cloud. The AngelQ system integrates quantum design automation (QDA) to achieve quantum and reversible circuit synthesis by a quantum-inspired optimization (QiO) technique and has visualization software interfaces to verify the QiO process and the correctness of the synthesized quantum and reversible circuits. First, the proposed novel QiO method has four significant features: Adaptive strategy, quantum-Not gate, update mechanism by Global solutions, and Entanglement Local search, named Angel QiO. which is a flexible technique to realize various circuits under different gate libraries with a few alterations. Angel QiO can construct diversified function-equivalent circuits to assess the circuit composition and boost the development of circuit synthesis. Second, researchers can observe the QiO algorithm process and inspect the intermediate result formula through AngelQ system’s visualization interface to further adjust the parameters and improve the performance. Moreover, it benefits beginners’ learning and adds convenience to education. In summary, the AngelQ system can extend and facilitate the future design and automation of quantum computing.

A Reverse Electromagnetic Force Suppression Circuit and Its Control Method for Reluctance Coil-Gun

To realize high-speed launch of reluctance coil-gun (RCG) requires the suppression of reverse electromagnetic (EM) force, when the center of the coil coincides with the center of the projectile to disconnect the coil power supply to quickly reduce the current is an effective means. In this study, the problems in the existing researches are explained in terms of circuit theory, and two technical difficulties are pointed out. One is to find the exact coincide time, which is basically estimated by the finite element method (FEM) at present, there are problems of slow calculation speed, and the results are affected by the accuracy of the input electrical parameters. Second, a sudden shutdown of a charged IGBT will create a large inductive electric potential and may be damaged. In this study, the treatment methods are proposed for these two points, respectively. On the one hand, an algorithm model is proposed to quickly estimate the coincide time based on the measured current data in the coil; compared with the FEM, it has the advantages of no need to know the electrical parameters and fast calculation speed. On the other hand, a new circuit topology is proposed, in which the IGBT is moved to the coil branch for current breaking at any time and a resistor–capacitor ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> ) absorption circuit is connected in parallel to the coil side to protect the IGBT. The comparison of experimental and simulation results proves that the method proposed in this study is feasible, and it avoids both the tedious operation of testing component parameters and the errors caused by inaccurate parameter input, showing the convenience in application.

A New Design of a 3 × 3 Reversible Circuit Based on a Nanoscale Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is the best-suggested nanotechnology for designing digital electronic circuits. It has a higher switching frequency, low-power expenditures, low area, high speed and higher scale integration. Recently, many types of research have been on the design of reversible logic gates. Nevertheless, a high demand exists for designing high-speed, high-performance and low-area QCA circuits. Reversible circuits have notably improved with developments in complementary metal–oxide–semiconductor (CMOS) and QCA technologies. In QCA systems, it is important to communicate with other circuits and reversible gates reliably. So, we have used efficient approaches for designing a [Formula: see text] reversible circuit based on XOR gates. Also, the suggested circuits can be widely used in reversible and high-performance systems. The suggested architecture for the [Formula: see text] reversible circuit in QCA is composed of 28 cells, occupying only 0.04[Formula: see text][Formula: see text]m2. Compared to the state-of-the-art, shorter time, smaller areas, more operational frequency and better performance are the essential benefits of the suggested reversible gate design. Full simulations have been conducted with the utilization of QCADesigner software. Additionally, the proposed [Formula: see text] gate has been schematized using two XOR gates.

Thiazolothiazole-Containing Conjugated Polymer with Electrochromism and Electrofluorochromism-Based Dual Performance for a Flip-Flop Molecular Logic Gate

Dual-performance devices based on electrochromism and electrofluorochromism have recently gained much attention in display technology. However, getting electrochromism and electrofluorochromism from the same material is very challenging. Herein, we have synthesized a low-band-gap donor–acceptor conjugated thiazolothiazole-containing organic polymer, P-TzTz, that exhibited a quasi-reversible single-electron reduction to demonstrate a pale yellow-to-black (NIR region) electrochromism and a red-to-quenched electrofluorochromism at a low potential window of −1.7 to +0.6 V with suitable electrochromic/electrofluorochromic parameters and stability. Possible redox-induced modulation of π–π* and intramolecular charge transfer in the P-TzTz polymer, which was validated through density functional theory calculations, interplayed the key role of tunable absorption from vis to NIR and on–off fluorescence switching. Finally, mimicking a flip-flop logic gate model with optical memory functions was also demonstrated by taking the potentials as inputs and electrochromic and electrofluorochromic dual performance signals as outputs.

Novel ultra-energy-efficient reversible designs of sequential logic quantum-dot cellular automata flip-flop circuits

Quantum-dot cellular automata (QCA) is a technological approach to implement digital circuits with exceptionally high integration density, high switching frequency, and low energy dissipation. QCA circuits are a potential solution to the energy dissipation issues created by shrinking microprocessors with ultra-high integration densities. Current QCA circuit designs are irreversible, yet reversible circuits are known to increase energy efficiency. Thus, the development of reversible QCA circuits will further reduce energy dissipation. This paper presents novel reversible and irreversible sequential QCA set/reset (SR), data (D), Jack Kilby (JK), and toggle (T) flip-flop designs based on the majority gate that utilizes the universal, standard, and efficient (USE) clocking scheme, which allows the implementation of feedback paths and easy routing for sequential QCA-based circuits. The simulation results confirm that the proposed reversible QCA USE sequential flip-flop circuits exhibit energy dissipation less than the Landauer energy limit. Irreversible QCA USE flip-flop designs, although having higher energy dissipation, sometimes have floorplan areas and delay times less than those of reversible designs; therefore, they are also explored. The trade-offs between the energy dissipation versus the area cost and delay time for the reversible and irreversible QCA circuits are examined comprehensively.

An efficient design and implementation of a reversible logic CCNOT (Toffoli) gate in QCA for nanotechnology

An efficient design and implementation of a reversible logic CCNOT (Toffoli) gate in QCA for nanotechnology

Simulation of reversible molecular mechanical logic gates and circuits.

Landauer's principle places a fundamental lower limit on the work required to perform a logically irreversible operation. Logically reversible gates provide a way to avoid these work costs and also simplify the task of making the computation as a whole thermodynamically reversible. The inherent reversibility of mechanical logic gates would make them good candidates for the design of practical logically reversible computing systems if not for the relatively large size and mass of such systems. In this paper we outline the design and simulation of reversible molecular mechanical logic gates that come close to the limits of thermodynamic reversibility even under the effects of thermal noise, and outline associated circuit components from which arbitrary combinatorial reversible circuits can be constructed and simulated. We demonstrate that isolated components can be operated in a thermodynamically reversible manner, and explore the complexities of combining components to implement more complex computations. Finally, we demonstrate a method to construct arbitrarily large reversible combinatorial circuits using multiple external controls and signal boosters with a working half-adder circuit.

A DNA Finite-State Machine Based on the Programmable Allosteric Strategy of DNAzyme.

Living organisms can produce corresponding functions by responding to external and internal stimuli, and this irritability plays a pivotal role in nature. Inspired by such natural temporal responses, the development and design of nanodevices with the ability to process time-related information could facilitate the development of molecular information processing systems. Here, we proposed a DNA finite-state machine that can dynamically respond to sequential stimuli signals. To build this state machine, a programmable allosteric strategy of DNAzyme was developed. This strategy performs the programmable control of DNAzyme conformation using a reconfigurable DNA hairpin. Based on this strategy, we first implemented a finite-state machine with two states. Through the modular design of the strategy, we further realized the finite-state machine with five states. The DNA finite-state machine endows molecular information systems with the ability of reversible logic control and order detection, which can be extended to more complex DNA computing and nanomachines to promote the development of dynamic nanotechnology.

A new design for XOR gate-based reversible double Feynman gate in nano-scale quantum-dots

Quantum-dot Cellular Automata (QCA), which provides a novel technique for fabricating energy-efficient nano-scale digital circuits, can replace transistor-based technologies. But, in this technology, designing a reliable and reversible circuit design is very important. The use of reversible logic gates in QCA has piqued the interest of a wide range of researchers. However, designing QCA-based architecture for reversible logic circuits still has ample space. The previous circuits in this field have some disadvantages, such as the lack of easy access to inputs and outputs, low speed, and a high number of consumed cells, which have caused the lack of expandability of circuits. Therefore, there is a need to design smaller and faster circuits with easier access to inputs and outputs so that in addition to achieving high speed, reversibility can be extended to other circuits as well. As a result, this study presents a helpful topology for implementing a reversible circuit based on the innovative XOR gate. In this design, a reversible circuit is designed using 2 two-input XOR gates, cell arrangement, and columbic repulsion. It can be integrated with other gates to test the performance of the circuit, its reversibility, and its expansion. To test the extendability of the proposed circuit, we also considered a 4-bit binary to gray code converter. The suggested ideas are tested by running simulations using the QCADesigner-E. The suggested construction consists of 19 cells and takes up only 0.03 µm2. The results confirmed that the design has stable and applicable size, cost, and structures. The proposed architecture is also simple to use on bigger circuits and offers easy access to input and output.

Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis

&lt;p&gt;&lt;span&gt;The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with high-performance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP multiplier is created using a 24x24 Wallace tree multiplier. In contrast, the reciprocal unit of the RFP divider is designed using Newton Raphson’s method. The RFPA unit and its submodules are executed in parallel by utilizing one clock cycle individually. The RFPA unit and its submodules are synthesized separately on the Vivado IDE environment and obtained the implementation results on Artix-7 field programmable gate array (FPGA). The RFPA unit utilizes only 18.44% slice look-up tables (LUTs) by consuming the 0.891 W total power on Artix-7 FPGA. The RFPA unit sub-models are compared with existing approaches with better performance metrics and chip resource utilization improvements.&lt;/span&gt;&lt;/p&gt;

Quantum algorithm for ESOP minimization

The Exclusive-OR Sum-of-Product (ESOP) minimization problem has long been of interest to the research community because of its importance in classical logic design (including low-power design and design for test), reversible logic synthesis, and knowledge discovery, among other applications. However, no exact minimal minimization method has been presented for more than seven variables on arbitrary functions. This paper presents a novel quantum-classical hybrid algorithm for the exact minimal ESOP minimization of incompletely specified Boolean functions. This algorithm constructs oracles from sets of constraints and leverages the quantum speedup offered by Grover's algorithm to find solutions to these oracles, thereby improving over classical algorithms. Improved encoding of ESOP expressions results in substantially fewer decision variables compared to many existing algorithms for many classes of Boolean functions. This paper also extends the idea of exact minimal ESOP minimization to additionally minimize the cost of realizing an ESOP expression as a quantum circuit. To the extent of the authors' knowledge, such a method has never been published. This algorithm was tested on completely and incompletely specified Boolean functions via quantum simulation.

Quantum rotational cryptanalysis for preimage recovery of round-reduced Keccak

The Exclusive-OR Sum-of-Product (ESOP) minimization problem has long been of interest to the research community because of its importance in classical logic design (including low-power design and design for test), reversible logic synthesis, and knowledge discovery, among other applications. However, no exact minimal minimization method has been presented for more than seven variables on arbitrary functions. This paper presents a novel quantum-classical hybrid algorithm for the exact minimal ESOP minimization of incompletely specified Boolean functions. This algorithm constructs oracles from sets of constraints and leverages the quantum speedup offered by Grover's algorithm to find solutions to these oracles, thereby improving over classical algorithms. Improved encoding of ESOP expressions results in substantially fewer decision variables compared to many existing algorithms for many classes of Boolean functions. This paper also extends the idea of exact minimal ESOP minimization to additionally minimize the cost of realizing an ESOP expression as a quantum circuit. To the extent of the authors' knowledge, such a method has never been published. This algorithm was tested on completely and incompletely specified Boolean functions via quantum simulation.

Novel Quantum-Dot Cellular Automata-Based Gate Designs for Efficient Reversible Computing

Reversible logic enables ultra-low power circuit design and quantum computation. Quantum-dot Cellular Automata (QCA) is the most promising technology considered to implement reversible circuits, mainly due to the correspondence between features of reversible and QCA circuits. This work aims to push forward the state-of-the-art of the QCA-based reversible circuits implementation by proposing a novel QCA design of a reversible full adder\full subtractor (FA\FS). At first, we consider an efficient XOR-gate, and based on this, new QCA circuit layouts of Feynman, Toffoli, Peres, PQR, TR, RUG, URG, RQCA, and RQG are proposed. The efficient XOR gate significantly reduces the required clock phases and circuit area. As a result, all the proposed reversible circuits are efficient regarding cell count, delay, and circuit area. Finally, based on the presented reversible gates, a novel QCA design of a reversible full adder\full subtractor (FA\FS) is proposed. Compared to the state-of-the-art circuits, the proposed QCA design of FA\FS reversible circuit achieved up to 57% area savings, with 46% and 29% reduction in cell number and delay, respectively.

Automatic generation of Grover quantum oracles for arbitrary data structures

The steadily growing research interest in quantum computing—together with the accompanying technological advances in the realization of quantum hardware—fuels the development of meaningful real-world applications, as well as implementations for well-known quantum algorithms. One of the most prominent examples till today is Grover’s algorithm, which can be used for efficient search in unstructured databases. Quantum oracles that are frequently masked as black boxes play an important role in Grover’s algorithm. Hence, the automatic generation of oracles is of paramount importance. Moreover, the automatic generation of the corresponding circuits for a Grover quantum oracle is deeply linked to the synthesis of reversible quantum logic, which—despite numerous advances in the field—still remains a challenge till today in terms of synthesizing efficient and scalable circuits for complex Boolean functions. In this paper, we present a flexible method for automatically encoding unstructured databases into oracles, which can then be efficiently searched with Grover’s algorithm. Furthermore, we develop a tailor-made method for quantum logic synthesis, which vastly improves circuit complexity over other current approaches. Finally, we present another logic synthesis method that considers the requirements of scaling onto real world backends. We compare our method with other approaches through evaluating the oracle generation for random databases and analyzing the resulting circuit complexities using various metrics.

Nano‐scale design of full adder and full subtractor using reversible logic based decoder circuit in quantum‐dot cellular automata

AbstractThis paper presents a reversible nano‐scale decoder circuit. The decoder is designed by utilizing the new quantum‐dot cellular automata (QCA) format of the QCA1 gate. This QCA1 gate provides 34.25% less cell count with 54.37% less area than the best existing designs. Thus, the proposed QCA1 gate provides less area considering the best existing state‐of‐the‐art plans. The IBMQ‐based quantum realization of the QCA1 gate is also illustrated. The reversible full adder and subtractor circuits by employing the proposed decoder are likewise explored in this paper. A four‐input reversible OR‐gate is structured and concatenates with a decoder circuit to frame the circuit for full adder and subtractor. The energy dissipation by these QCA circuits is assessed to build up that QCA is an attractive option to CMOS for realizing reversible logic designs. The implemented results are compared with the truth table to ensure operational accuracy. The planned circuits can be utilized to structure reversible designs for nano‐communication.

A new design of parity preserving reversible Vedic multiplier targeting emerging quantum circuits

AbstractReversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.

Gigahertz Sub-Landauer Momentum Computing

We introduce a fast and highly efficient physically realizable bit swap. Employing readily available and scalable Josephson junction microtechnology, the design implements the recently introduced paradigm of momentum computing. Its nanosecond speeds and sub-Landauer thermodynamic efficiency arise from dynamically storing memory in momentum degrees of freedom. As such, during the swap, the microstate distribution is never near equilibrium and the memory-state dynamics fall far outside of stochastic thermodynamics that assumes detailed-balanced Markovian dynamics. The device implements a bit-swap operation---a fundamental operation necessary to build reversible universal computing. Extensive, physically calibrated simulations demonstrate that device performance is robust and that momentum computing can support thermodynamically efficient, high-speed, large-scale general-purpose computing that circumvents Landauer's bound.

Quantum reversible circuits for $${\text {GF}}(2^8)$$ multiplication based on composite field arithmetic operations

Quantum reversible circuits for $${\text {GF}}(2^8)$$ multiplication based on composite field arithmetic operations

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two’s complement (B2C) and MUX circuits, while DesignII combines binary two’s complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-of-the-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.