Reversible Adder Research Articles

Design of Prefix Adder Amalgamation Reversible Logic Gates using 16 Bit Kogge Stone Adder

Objective: VLSI integer adders are critical elements in general purposed DSP and DSPA processors. These used in design of ALU, floating point arithmetic data paths and address generation units. Parallel prefix adders rely on simple cell design. Modern FPGAs utilize fast carry chain for optimization ripple carry adder. Methods/Analysis: Design of the delay models and cost analysis by VLSI embedded system is done in this paper. Prefix adder with reversible logic gates utilizing 16 bit kogge stone adder have been design using PERES logic. Findings: Methodology is based on the fact that a parallel prefix adder can be represented as a graph consists of carry operator nodes. The adder structure has minimum logic depth and binary tree structure with minimum fan-out. From the simulate results this is formed that computational path net delay for 16 X16 bit prefix adder using reversible logic is 20.828 ns with Kogge Stone Adder is reading to 17.247ns. Novelty/Improvement: The multiple based on 16 bit Kogge Stone Adder is formed to be less efficient than the case of reversible adder in term of delay and power analysis.

Design and Implementation of Adders using Novel Reversible Gates in Quantum Cellular Automata

Background/Objectives: The objective is to reduce the Quantum Cost (QC), Garbage Output (GO) and Gate Counts in the design of the adder by incorporating the Novel Reversible Gates. Methods/Statistical Analysis: In recent day's energy dissipation is the major complex problem in circuit designing in order to recede this problem the reversible logic is employed, where the input vectors can be derived from the output vectors and from the output vectors the input vectors can be procured. Using this technique the Quantum Cost, Garbage Outputs and Gate Counts of the design is reduced. Findings: Based on the technique of reversible logic a novel reversible Gates is proposed from that the novel reversible adders have been designed. The novel reversible gates satisfy the property of reversibility and universality which shows the uniqueness of the proposed gates. The comparative analysis have been made with the existing work, the proposed work shows a significant improvement in the design optimization parameters. Application/Improvements: The proposed structures can be employed in the ALU design and in Floating Point Multiplier design. The comparative analysis shows that Number of Gates, Garbage Outputs and Quantum Cost is minimum for the proposed gate based structure rather than conventional one

Novel design of nanometric reversible floating point adder with parity preservation capability

Reversible logic is a new theme of study that requires reversible logic circuits and plays a vital role in quantum computing, low power CMOS and nanotechnology. Parity preserving is one of the oldest procedures for the extension of fault tolerant systems. Floating-point addition is one of the most complicated computer arithmetic operations. There are many reversible implementations of logical and arithmetic units like ALU, multiplier, adder, etc., but few designs for reversible floating-point adder exist. In this paper, we present parity preserving reversible floating-point adder design with nanometric scale for the first time. Also, we present a parity preserving reversible gate. At the end, the final results are reported. All the scales are in nanometric area.

A novel reversible carry-selected adder with low latency

ABSTRACTReversible logic is getting more and more attention in quantum computing, optical computing, nanotechnology and low-power complementary metal oxide semiconductor designs since reversible circuits do not loose information during computation and have only small energy dissipation. In this paper, a novel carry-selected reversible adder is proposed primarily optimised for low latency. A 4-bit reversible full adder with two kinds of outputs, minimum delay and optimal quantum cost is presented as the building block for -bit reversible adder. Three new reversible gates NPG (new Peres gate), TEPG (triple extension of Peres gate) and RMUX21 (reversible 2-to-1 multiplexer) are proposed and utilised to design efficient adder units. The secondary carry propagation chain is carefully designed to reduce the time consumption. The novelty of the proposed design is the consideration of low latency. The comparative study shows that the proposed adder achieves the improvement from 61.46% to 95.29% in delay over the existing designs.

ASIC Design of Reversible Adder and Multiplier

ABSTRACT Reversible logic is one of the promising research areas in low power applications such as quantum computing, optical information processing and low power CMOS design. In this paper we present a reversible carry look ahead adder and an array multiplier. The circuits are designed such that they result in less garbage outputs, constant inputs, and less gate count compared to previous existing designs. We also gain better improvements in terms of power and area when compared to conventional adders and multipliers. The implemented designs are simulated using NC launch and synthesized by RTL compiler. Keywords Reversible, Garbage constant, Garbage output. 1. INTRODUCTION Power dissipation is one of the important problems faced now a day in VLSI design [4]. The combinational circuit dissipates KTlog 2 [1] Joules of heat for every bit of information to be lasted, irrespective of the technology used .where K is Boltzmann constant and T is temperature. Heat dissipation reduces the life span of the circuits. The information is lost when input bits are not able to recover from the output vectors. Reversible gates naturally take care of heat, since input vectors are uniquely recovered from the output vectors. That is there is one-to-one correspondence between input vectors and output vectors. Each output of the Reversible gates is used once, that is the Reversible circuit is feedback free. Some of the terms related to Reversible logic are [2, 3].

Novel designs for fault tolerant reversible binary coded decimal adders

Reversible logic circuits have received emerging attentions in recent years. Reversible logic is widely applied in some new technical fields, such as quantum computing, nanocomputing and optical computing and so on. In this paper, three fault tolerant gates are proposed, ZPL gate, ZQC gate and ZC gate. By using the proposed gates, fault tolerant quantum and reversible BCD adder and skip carry BCD adder are designed, which overcome the limitations of the existing methods. The proposed reversible BCD adders have also parity-preserving property. They are better than the existing counterparts, especially in the quantum cost. Proposed designs have been compared with existing designs with respect to the number of gates, number of garbage outputs and quantum cost.

Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA

Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.

Optimization and Implementation of Reversible BCD Adder in Terms of Number of Lines

Optimization and Implementation of Reversible BCD Adder in Terms of Number of Lines

Designing novel reversible BCD adder and parallel adder/subtraction using new reversible logic gates

Reversible logic has received much attention in recent years when calculation with minimum energy consumption is considered. Especially, interest is sparked in reversible logic by its applications in some technologies, such as quantum computing, low-power CMOS design, optical information processing and nanotechnology. This article proposes two new reversible logic gates, ZRQ and NC. The first gate ZRQ not only implements all Boolean functions but also can be used to design optimised adder/subtraction architectures. One of the prominent functionalities of the proposed ZRQ gate is that it can work by itself as a reversible full adder/subtraction unit. The second gate NC can complete overflow detection logic of Binary Coded Decimal (BCD) adder. This article proposes two approaches to design novel reversible BCD adder using new reversible gates. A comparative result which is presented shows that the proposed designs are more optimised in terms of number of gates, garbage outputs, quantum costs and unit delays than the existing designs.

Design of Hybrid Adder-Subtractor (HAS) using Reversible Logic Gates in QCA

Quantum computers for the efficient simulation of physical systems are emerging today. Effect of Spin on Quantum Dots (QDs) paved the way for QCA. Quantum-dot cellular automata (QCA) have a simple cell as the basic element. The cell is used as a building block to construct gates and wires.Reversible logic has extensive applications in quantum Computing. Reversible logic is widely being considered as the potential logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on physical entropy. Reversible gates such as Fredkin and DKG gates can be of great use for the implementation of the logic designs. Recent advances in reversible logic allow for improved quantum computer algorithms and schemes for corresponding computer architectures.In this paper, a design constructing the hybrid adder - Subtractor based on reversible logic gates as logic components using QCA is proposed. By using reversible logic gates instead of using traditional logic gates such as AND, OR, XOR, NOT, a Hybrid reversible Adder - Subtractor whose function is the same as the traditional Adder and Subtractor are designed and compared with the functioning of DKG gate based adder-subtractor. The simulation results shows that higher speed, smaller size and lower power consumption can be achieved with the proposed HAS system.

A New Design Technique of Reversible BCD Adder Based on NMOS with Pass Transistor Gates

In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.

A novel nanometric fault tolerant reversible divider

Quantum and reversible logic circuits have more advantages than the common circuits, like low power consumption. These circuits are good choice to design future computers. One of the important issues in reversible logic is parity preservation. If parity of inputs and outputs are equal in reversible gate, this gate will be parity preserve. Reversible circuits made by these gates are parity preserve. In this paper we propose a new fault tolerant reversible divider. The proposed fault tolerant reversible divider is the first effort to design fault tolerant reversible division circuit. In this circuit, we use some fault tolerant reversible components like fault tolerant reversible parallel adder, fault tolerant reversible shift register and fault tolerant reversible n-bit register. Hence, we also propose a new fault tolerant reversible full adder, a new fault tolerant reversible n+1-bit parallel adder and a new basic cell for PIPO fault tolerant reversible left-shift register. These parity preserving reversible components are also proposed for the first time in the literature. All the scales are in the nanometric area. Key words: Reversible logic, parity preservation, fault tolerant, nanometric circuits, reversible divider.

Implementation of 4-bit Reversible Parallel Adder Using Nanoelectronic Single-Electron Circuitry

Single-Electron devices imply the possibility to control the movement and position of a single electron or a few electrons thereby reducing the device size and power consumption. A single-electron transistor can be operated as a switch with the transition of the gate voltage between two appropriate values thereby modifying conventional logic design into the single-electron regime by simply exchanging MOSFETs with SETs. Single-electron logic circuits can thus be employed to perform arithmetic functions, thereby making single-electron technology viable to realize high density low power consumping VLSI circuits. In the present work a single electron logic based high speed power efficient 4-bit reversible binary parallel adder is designed, implemented and its performance studied on its simulated model.

PARALLELIZATION OF REVERSIBLE RIPPLE-CARRY ADDERS

The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of garbage. Here, we present a novel parallelization scheme wherein m parallel k-bit reversible ripple-carry adders are combined to form a reversible mk-bit ripple-block carry adder with logic depth [Formula: see text] for a minimal logic depth [Formula: see text], thus improving on the mk-bit ripple-carry adder logic depth [Formula: see text]. The underlying mechanisms of the parallelization scheme are formally proven correct. We also show designs for garbage-less reversible comparison circuits. We compare the circuit costs of the resulting ripple-block carry adder with known optimized reversible ripple-carry adders in measures of circuit delay, width, gate, transistor count, and relative power efficiency, and find that the parallelized adder offers significant speedups at realistic word sizes with modest parallelization overhead.

Optimized reversible binary-coded decimal adders

Babu and Chowdhury [H.M.H. Babu, A.R. Chowdhury, Design of a compact reversible binary coded decimal adder circuit, Journal of Systems Architecture 52 (5) (2006) 272-282] recently proposed, in this journal, a reversible adder for binary-coded decimals. This paper corrects and optimizes their design. The optimized 1-decimal BCD full-adder, a 13x13 reversible logic circuit, is faster, and has lower circuit cost and less garbage bits. It can be used to build a fast reversible m-decimal BCD full-adder that has a delay of only m+17 low-power reversible CMOS gates. For a 32-decimal (128-bit) BCD addition, the circuit delay of 49 gates is significantly lower than is the number of bits used for the BCD representation. A complete set of reversible half- and full-adders for n-bit binary numbers and m-decimal BCD numbers is presented. The results show that special-purpose design pays off in reversible logic design by drastically reducing the number of garbage bits. Specialized designs benefit from support by reversible logic synthesis. All circuit components required for optimizing the original design could also be synthesized successfully by an implementation of an existing synthesis algorithm.

Canonical realization and round‐off noise analysis for combinatorial filters

AbstractRecent developments in memory devices have led to the proposal of a direct method of constructing combinatorial logic filter which uses bit serial operation (i.e., memory and reversible adder are used for bitwise summing of the result of weighted addition). By combinatorial construction it is possible to increase operating speed, simplify the hardware and decrease the power consumption, leading to an efficient digital filter. This paper applies bit serial operation to the canonical construction, leading to a combinatorial filter with memory capacity of 1/2N‐1. Then, bit parallel‐serial operation, which sums up the result of multibit weighted addition, is applied to the canonical construction of the second‐order section, leading to a digital filter with t/I times higher speed than in the past. It is noted that the roundoff noise in the combinatorial filter is independent of the input data, and a noise evaluation model is proposed in which the error can be independently discussed. Using the proposed model, the mean‐square error of the filter output can easily be determined. This paper deals with the drawbacks in the past theory of noise evaluation for the direct construction and performs a noise analysis for the canonical construction. The result is useful in application to LSI design for a high‐speed digital filter.