Abstract
AbstractRecent developments in memory devices have led to the proposal of a direct method of constructing combinatorial logic filter which uses bit serial operation (i.e., memory and reversible adder are used for bitwise summing of the result of weighted addition). By combinatorial construction it is possible to increase operating speed, simplify the hardware and decrease the power consumption, leading to an efficient digital filter. This paper applies bit serial operation to the canonical construction, leading to a combinatorial filter with memory capacity of 1/2N‐1. Then, bit parallel‐serial operation, which sums up the result of multibit weighted addition, is applied to the canonical construction of the second‐order section, leading to a digital filter with t/I times higher speed than in the past. It is noted that the roundoff noise in the combinatorial filter is independent of the input data, and a noise evaluation model is proposed in which the error can be independently discussed. Using the proposed model, the mean‐square error of the filter output can easily be determined. This paper deals with the drawbacks in the past theory of noise evaluation for the direct construction and performs a noise analysis for the canonical construction. The result is useful in application to LSI design for a high‐speed digital filter.
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