High density flash memory is based on layered dielectric including charge trapping layers [1]. Device scaling can be facilitated by decreasing equivalent electrical thickness of the layered dielectric, which also induces degradation of charge retention. Moreover, the thickness combination of each dielectrics need to be optimized to give minimum charge loss at zero applied voltage (power-off condition). The optimal thickness combination can be experimentally found by characterizing bias dependent charge loss, at which combination, thickness scaling limitation for a given layered dielectric can be established. By applying higher dielectric constant materials, the equivalent electrical thickness of the layered dielectric can be reduced; where additional materials engineering is necessary. In this work, we have applied various compositional alloys of HfO2 and AlO2, and their spatial grading. As a result, it is shown that high post-deposition process temperature critically induces charge retention degradation, and the physical reasoning of compositional and spatial grading optimization is obtained for minimum charge losses. In addition, optimal thickness combination for minimum charge loss at zero bias is formulated supported by experimental evidence. Moreover, high energy edge of trap states are extracted from charge loss characteristics, which are compared for various dielectric materials and bias conditions. Keywords: dielectric; charge trap; flash memory. Acknowledgements This work was supported by NRF grant (NRF-2017R1D1A1B03029764) funded by Korean Government. Reference S. Choi, S. J. Baik, J.-T. Moon, Technical Digest of International Electron Device Meeting 2008, 2008, 925-928. Figure 1